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| promach | How much RAM does building nextpnr require ? 8GB RAM plus 5GB swap also fail to build | 02:15 |
|---|---|---|
| cr1901_modern | At least 2GB IME, and even then on -j1 you will go to swap | 02:23 |
| cr1901_modern | It's a pity, can't build on my ARM SBCs, and the Pinebook takes hours | 02:24 |
| promach | I already had 8GB RAM | 02:25 |
| cr1901_modern | I assume you're building -j$NPROC | 02:25 |
| cr1901_modern | if you're building w/ -j1, then WOW ._. | 02:25 |
| promach | cr1901_modern : how long does it take for -j$NPROC ? and only use 2GB ? | 02:30 |
| cr1901_modern | If you use -j1, you can do it in 2GB of RAM and 2GB of swap | 02:31 |
| cr1901_modern | I have no idea how much -j$NPROC takes, but 8GB RAM seems extremely high | 02:31 |
| promach | -j$NPROC should use less time and RAM, I suppose ? | 02:33 |
| promach | cr1901_modern | 02:33 |
| cr1901_modern | Less time, more RAM | 02:33 |
| cr1901_modern | nevermind, I don't know what the problem is | 02:34 |
| cr1901_modern | sorry | 02:34 |
| promach | ok | 02:34 |
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| pepijndevos_ | Are there any public liberty files I can look at as a reference? | 17:39 |
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| corecode | what do you mean by liberty files? | 18:00 |
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| pepijndevos_ | corecode, a library that describes asic logic cells | 18:04 |
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| pepijndevos_ | Warning: Found unsupported expression 'D*C' in pin attribute of cell '74AC575_8x1DFFR' - skipping. | 19:23 |
| pepijndevos_ | Doesn't seem like Yosys supports synchronous reset flip-flops? | 19:24 |
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| ZirconiumX | Possibly one for daveshah: you can use `sat` to prove two netlists are equivalent, right? | 19:37 |
| ZirconiumX | I don't think netlist is at all the right term; I mean "an internally represented ILANG design" | 19:38 |
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| pepijndevos_ | lol, for the pwm benchmark, almost all of the chips are used to say x>y | 19:44 |
| ZirconiumX | pepijndevos_: I made a pass to convert chips into 7485s | 19:45 |
| ZirconiumX | *convert comparison chips | 19:45 |
| ZirconiumX | It was marginally worse for me, but I can commit it if you want | 19:46 |
| ZirconiumX | Hmm, I wonder if it's better to use 7485s for variable comparisons and let ABC handle comparison to a constant | 19:47 |
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| ZirconiumX | pepijndevos_: do you mind conducting an experiment for me? | 19:49 |
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| pepijndevos_ | ZirconiumX, not at all | 19:59 |
| pepijndevos_ | What do you think about adding a 74181, maybe as an $alu thingy? | 20:01 |
| pepijndevos_ | * as long as your experiment allows me to go to bed before 11 | 20:01 |
| ZirconiumX | Can you quickly scratch up a 32 bit comparison module between two variables, a variable and zero, and a variable and some random binary number? | 20:01 |
| ZirconiumX | And then `synth` them | 20:01 |
| ZirconiumX | Here's my hunch: comparison with zero will be smallest, then the comparison with the random number, and then the variable comparison | 20:02 |
| pepijndevos_ | I'll try. My verilog skills are basically non-existant. (learned VHDL in uni) | 20:02 |
| ZirconiumX | pepijndevos_: nak on including a 74181 as an $alu cell; the inputs of the $alu cell are very different to what the 74181 expects | 20:04 |
| ZirconiumX | But you could include the various functions as liberty cells | 20:04 |
| ZirconiumX | The 74182 should make a good $lcu though | 20:04 |
| pepijndevos_ | I thought liberty cells did not works for more than one output | 20:05 |
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| pepijndevos_ | But yea, was thinking if we could complement the $add techpass with some other arithemitic. | 20:06 |
| ZirconiumX | Ah, good point | 20:06 |
| ZirconiumX | Hmm | 20:06 |
| ZirconiumX | So | 20:06 |
| ZirconiumX | The 74181 would be wonderful | 20:06 |
| ZirconiumX | *but* it's also difficult to obtain | 20:06 |
| ZirconiumX | Which was why I picked a 283 | 20:07 |
| pepijndevos_ | oh... did not know that | 20:07 |
| pepijndevos_ | what's a $lcu? | 20:07 |
| pepijndevos_ | The manual just has a fixme | 20:07 |
| ZirconiumX | Lookahead carry unit | 20:08 |
| ZirconiumX | The 283 is (usually?) a carry-skip adder, but an adder with an LCU is far superior | 20:09 |
| pepijndevos_ | Would it make sense to implement $sub with a quad inverter and carry in tied high? | 20:10 |
| ZirconiumX | The '181 has /P and /G specifically to integrate with a '182 | 20:10 |
| ZirconiumX | I'm reasonably sure Yosys knows how to do that already | 20:10 |
| pepijndevos_ | Hmm, so far subtraction generated a bunch of xor stuff for me | 20:11 |
| ZirconiumX | Hmm, okay | 20:11 |
| ZirconiumX | In that case, sure | 20:11 |
| pepijndevos_ | Eh... I'll get back to your compare test. Maybe I'll make an issue to collect ALU thoughts. | 20:12 |
| ZirconiumX | Sure thing | 20:13 |
| pepijndevos_ | So... 0 is actually smaller than the particular random number I picked | 20:15 |
| pepijndevos_ | But with a variable is many times bigger | 20:15 |
| pepijndevos_ | for any number 60-70, for the variable 196. | 20:16 |
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| corecode | the gigatron does alu with mux chips | 20:25 |
| corecode | it's a mind bender | 20:25 |
| pepijndevos_ | Yea, I remember in the video they explained their ALU uses 6 chips, but they did not go into details | 20:29 |
| pepijndevos_ | Because it'd be a whole seperate video I guess... | 20:29 |
| corecode | yea i just stared at the schematic until it made sense | 20:34 |
| pepijndevos_ | I wonder if maybe $sub -> $add+inv is maybe just some pass/parameter we're missing... | 20:34 |
| pepijndevos_ | corecode, IIRC it was based on another thing... maybe there is an article out there that explains it... or I need to find some time to stare at the schematic too. | 20:35 |
| pepijndevos_ | Is it *just* muxes? | 20:35 |
| corecode | and one adder, i think | 20:36 |
| corecode | or two? | 20:36 |
| ZirconiumX | pepijndevos_: It's not all that complex | 20:42 |
| ZirconiumX | The ALU of the Gigatron is essentially F(A) + F(B) | 20:43 |
| ZirconiumX | Sorry, Fa(A, B) + Fb(A, B) | 20:43 |
| ZirconiumX | Where Fa and Fb are 4-bit LUTs | 20:46 |
| ZirconiumX | implemented as 74153s | 20:46 |
| ZirconiumX | s/as/with/ | 20:46 |
| ZirconiumX | So addition is Fa(A, B) = A, and Fb(A, B) = B | 20:47 |
| ZirconiumX | subtraction is Fa(A, B) = A, Fb(A, B) = ~B and the carry-in is set high | 20:47 |
| ZirconiumX | And for most boolean logic, e.g. AND: Fa(A, B) = A & B, Fb(A, B) = 0 | 20:48 |
| ZirconiumX | corecode: ^ | 20:48 |
| pepijndevos_ | Sweet | 20:48 |
| ZirconiumX | So, you *could* implement an ALU in terms of muxes and addition | 20:49 |
| ZirconiumX | However, it quickly grows a bit inefficient | 20:49 |
| ZirconiumX | Because you need N 74153s and N/4 74283s | 20:50 |
| ZirconiumX | For an N-bit ALU | 20:50 |
| ZirconiumX | It's more flexible than a '181/'182 set up, but also bigger | 20:52 |
| pepijndevos_ | So how did the gigatron get away with 6 chips for its ALU (IIRC)? | 20:53 |
| ZirconiumX | pepijndevos_: They didn't; https://cdn.hackaday.io/files/20781889094304/Schematics.pdf page 6 shows they use 10 ICs for the ALU | 21:00 |
| ZirconiumX | It's an 8-bit ALU, so 8 74153s plus 8/4 = 2 74283s | 21:00 |
| pepijndevos_ | IRI (I recalled incorrectly) | 21:02 |
| ZirconiumX | The genius of the design comes to one Dieter Muller, AKA ttlworks | 21:03 |
| ZirconiumX | Who basically *wrote the book* on 74 series logic | 21:03 |
| ZirconiumX | http://www.6502.org/users/dieter/a1/a1_1.htm | 21:04 |
| tpb | Title: PAL16L8 (at www.6502.org) | 21:04 |
| pepijndevos_ | There is a book?? I need this | 21:04 |
| pepijndevos_ | for reasons | 21:04 |
| ZirconiumX | And more generally: http://www.6502.org/users/dieter/index.htm | 21:05 |
| tpb | Title: TAF (at www.6502.org) | 21:05 |
| pepijndevos_ | Too sleepy. Will look tomorrow. After... ahem, studying for the oral exam thursday heh | 21:07 |
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