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| azonenberg | ZirconiumX: down the road i want to build a 2-way superscalar, hyperthreaded rv32i core to see how fast i can push it | 00:13 |
|---|---|---|
| azonenberg | in-order though, i'm not trying to be BOOM | 00:13 |
| azonenberg | i also want to try to build something tiny and size optimized a la picorv32, maybe even start with the picorv32 design, but hand tune it with RPMs to try and squeeze the max clock rate and least area i can out of it | 00:14 |
| ZirconiumX | azonenberg: I think there's potential in a very wide in-order core, akin to what Nvidia are trying with Carmel. | 00:14 |
| azonenberg | So, i have another design that isnt riscv based that i want to get back to | 00:15 |
| ZirconiumX | I presume you've heard of SERV | 00:15 |
| azonenberg | it's 3 IPC VLIW but all instructions are ternary and the pipeline is Y-shaped | 00:15 |
| azonenberg | specifically meant for cryptographic code | 00:15 |
| azonenberg | no integers, possibly not even arbitrary branching | 00:15 |
| azonenberg | it's meant to be a black box sitting between a tcp/ip stack and application layer, or similar | 00:16 |
| azonenberg | but trying to be agile enough that you can load new algorithms in the future rather than being tied to e.g. AES | 00:16 |
| azonenberg | and with guaranteed single cycle execution of all instruction, no caches, no timing side channels | 00:16 |
| azonenberg | dedicated rom/ram for instructions, memory mapped fifo for tx/rx data, constant storage/sbox rom, and scratchpad for temporary state | 00:17 |
| azonenberg | Basically there's three ALUs that each do r32 op r32 op imm32 | 00:17 |
| azonenberg | except the third one operates on the output of the first two, instead of registers | 00:17 |
| azonenberg | so you only need one regfile write port despite doing 3 or 5 IPC (depending on if you count a ternary operation as one or two "instructions") | 00:18 |
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| ZirconiumX | CPU architecture is a very interesting thing | 00:20 |
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| azonenberg_mobil | interesting indeed | 01:16 |
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| trmm | back on the LPF versus parameters in the verilog; which one wins? if the LPF has a drive strength or slew rate, can the verilog override it? | 09:41 |
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| ZirconiumX | Right, I *believe* I have a live value table implementation | 11:49 |
| ZirconiumX | Or at least part of one | 11:53 |
| ZirconiumX | Is it preferable to use symbiyosys or yosys-smtbmc? | 12:07 |
| ZirconiumX | (maybe a question for ZipCPU) | 12:07 |
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| ZipCPU | SymbiYosys | 12:32 |
| ZipCPU | It's much simpler than yosys-smtbmc, gives you access to more solvers, and handles formats and format conversions for you | 12:32 |
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| maikmerten | my HX8K dev board keeps growing wings: https://pasteboard.co/IkMO5UO.jpg | 19:30 |
| tpb | Title: Pasteboard - Uploaded Image (at pasteboard.co) | 19:30 |
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| * ZirconiumX sighs | 20:39 | |
| ZirconiumX | I really don't understand formal methods | 20:40 |
| ZirconiumX | I've read a lot of articles on it | 20:40 |
| ZirconiumX | But I just don't 'get' it | 20:40 |
| ZirconiumX | I can't even prove that after reset my program counter points to the reset address | 20:41 |
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| ZirconiumX | pepijndevos: you ever looked at bit-serial architecture? | 21:03 |
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