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| ZirconiumX | ABC has such wonderful error messages when you mess up the Liberty file | 15:36 |
|---|---|---|
| ZirconiumX | https://pastebin.com/d2Rz9neu | 15:36 |
| tpb | Title: 25.1.1. Executing ABC. Running ABC command: /yosys-abc -s -f (at pastebin.com) | 15:36 |
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| ZirconiumX | daveshah: What's the difference between a $eq and $eqx cell? | 17:05 |
| ZipCPU | ZirconiumX: Try running "help $eqx+" and "help $eq+" within yosys | 17:07 |
| ZipCPU | Looks like the difference is "==" for $eq, and "===" for $eqz | 17:08 |
| ZirconiumX | Yeah | 17:08 |
| ZirconiumX | So $eqx includes don't-care cells | 17:09 |
| ZirconiumX | Or, well, 4-state | 17:09 |
| ZipCPU | You could argue that they both do, they just do different things with them | 17:09 |
| ZirconiumX | I think it's more correct for me to override $eq cells rather than $eqx cells | 17:10 |
| ZipCPU | It would help if you only had one type | 17:10 |
| ZirconiumX | Because I'm not smart enough to know the implications of trying to compare don't care values for equality | 17:11 |
| ZirconiumX | Apparently adding equality comparators is a fairly significant loss. Wonder what I messed up. | 17:43 |
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| daveshah | The problem at the moment is that ABC doesn't optimise around hard blocks | 17:59 |
| daveshah | A lot of the equality optimisations early on are probably significantly optimised by ABC when mapping as soft logic | 18:00 |
| daveshah | This is lost when you start to map things to hard blocks | 18:00 |
| ZirconiumX | Yeah, that's understandable | 18:05 |
| ZirconiumX | But comparison is a bit harder to optimise, right? | 18:08 |
| pepijndevos | \me waves at ZirconiumX and daveshah | 19:01 |
| ZirconiumX | Forward slash, not back | 19:01 |
| ZirconiumX | :P | 19:01 |
| daveshah | Hi pepijndevos! | 19:01 |
| ZirconiumX | But yeah, hello | 19:02 |
| * pepijndevos facepalms | 19:02 | |
| ZirconiumX | I'm the crazy person trying to get Yosys to synthesise for 7400 logic | 19:03 |
| pepijndevos | And I'm the crazy person cheering you on and playing with it instead of studying for my exams ;) | 19:06 |
| pepijndevos | It is not entirely unlikely that the majority of my summer holiday will be spent getting to the point where I can build a CPU in VHDL. | 19:07 |
| ZirconiumX | pepijndevos: You should really do your exams, let me be the one who wastes their summer holiday | 19:10 |
| ZirconiumX | I have entirely too much of it | 19:10 |
| pepijndevos | Oh, don't worry, my exams will be fine if I don't study in all the weekends and evenings. | 19:12 |
| pepijndevos | Thoug I'm very curious how you can have too much holiday. The list of projects I want to do is almost endless, and some of them would take years. Or have... | 19:13 |
| ZirconiumX | It's too much when you start going stir-crazy about halfway through | 19:14 |
| pepijndevos | Hum, as long as I remember to go outside and talk to some friends it tends to be fine for me. | 19:15 |
| ZirconiumX | My friends are pretty far away | 19:16 |
| pepijndevos | Hrm. That sucks. I kinda have this problem a bit too because at the university I pretty much made friends with the foreigners because they seemed more motivated than the dutch guys, but they all go to their parents for the summer. | 19:18 |
| pepijndevos | Talking about dutch... why is the chess program on your github called dorpsgek? | 19:20 |
| ZirconiumX | Because it behaves precisely as it is named :P | 19:20 |
| ZirconiumX | And also a classically British self-deprecating humour joke | 19:21 |
| pepijndevos | ... so can I ask if you are a brit who speaks dutch or a dutchy who likes british humor? | 19:23 |
| ZirconiumX | Ja. | 19:23 |
| ZirconiumX | :P | 19:23 |
| pepijndevos | Are you are a brit who speaks dutch or a dutchy who likes british humor? :P | 19:23 |
| ZirconiumX | Ja. | 19:24 |
| * pepijndevos facepalms | 19:24 | |
| ZirconiumX | Too easy, pepijndevos. | 19:24 |
| ZirconiumX | I'm a Brit, but while I can't speak any other language, I do have an interest in language in general | 19:25 |
| pepijndevos | Yay | 19:26 |
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| ZirconiumX | It helps that I have a lot of friends from across Europe | 19:29 |
| pepijndevos | While I'm eating my dinner, I'm trying to decide what's more fun, get this counter extraction pass to work, make GHDL work, or generate a KiCad netlist. | 19:30 |
| ZirconiumX | I think the counter extraction pass would need to be more general to properly work with e.g. '161s | 19:30 |
| pepijndevos | General in what sense? Except that it only counts down... | 19:31 |
| ZirconiumX | Being able to count up would be one useful case of it being more general | 19:32 |
| pepijndevos | Certainly XD | 19:33 |
| pepijndevos | Seems kiiinda doable to implement though. But maybe not very important right now. It's just that I want my CPU to have a stack, so a counter seems the way to go. | 19:34 |
| ZirconiumX | Well, a program counter would be a useful place for a '161 | 19:35 |
| pepijndevos | Yea, but having an adder and dff is not the end of the world for now. | 19:36 |
| pepijndevos | I think the KiCad netlist is the more rewarding thing to try, so you can actually implement your designs. | 19:38 |
| pepijndevos | What is your end goal with this project actually? | 19:42 |
| pepijndevos | If there is such a thing... | 19:42 |
| ZirconiumX | pepijndevos: I'd like to build a RISC-V CPU, but I realise how infeasible that would likely end up being | 19:43 |
| pepijndevos | Have you done any back-of-the-envelope calculations on the theorectial minimum number of chips you'd need? | 19:44 |
| ZirconiumX | A handful, and the answer is "quite a lot", but I'm no 74xx expert | 19:45 |
| pepijndevos | I'm trying to figure out how much chips the original 74xx computers had | 19:48 |
| pepijndevos | and failing... | 19:52 |
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| daveshah | Have you seen SERV? It's a bit serial RISC-V | 19:59 |
| pepijndevos | Hmmm, Yosys can generate a Spice netlist. What does it take to simulate that? | 20:00 |
| daveshah | SPICE models for the cells you've mapped to and a suitable simulator | 20:01 |
| daveshah | There's an example using ngspice here: https://github.com/YosysHQ/yosys/tree/master/examples/cmos | 20:02 |
| tpb | Title: yosys/examples/cmos at master · YosysHQ/yosys · GitHub (at github.com) | 20:02 |
| pepijndevos | Hmmm, fascinating. I think I found a 74xx spice library somewhere, so with a bit of renaming that might not be too hard. | 20:05 |
| pepijndevos | Warning: no (blackbox) module for cell type `\74AC16373_16x1DFF' (blinking.$auto$simplemap.cc:420:simplemap_dff$53) found! Guessing order of ports. | 20:05 |
| ZirconiumX | Huh, never gotten that error before | 20:08 |
| ZirconiumX | Well, warning | 20:08 |
| pepijndevos | I get that when generating spice. Probably same for generating low-level verilog? So I suppose models of all the cells are needed for simulation. | 20:09 |
| ZirconiumX | I would assume so, yeah | 20:09 |
| pepijndevos | Would be kinda... useful to simulate in various way before I go and order a PCB hehe | 20:10 |
| ZirconiumX | Fair warning, I tend to switch between tasks a lot | 20:10 |
| pepijndevos | Sounds not unfamiliar... | 20:11 |
| pepijndevos | I'll continue playing tomorrow and send PR's if I get anything useful. | 20:12 |
| ZirconiumX | Sure thing | 20:12 |
| pepijndevos | What would be nice is if Yosys could generate Verilog from the liberty code... | 20:20 |
| pepijndevos | Oh, it can | 20:24 |
| pepijndevos | read_liberty blah.lib write_verilog blah.v and boom | 20:24 |
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| pepijndevos | Also maybe relevant: https://groups.yahoo.com/neo/groups/LTspice/files/%20Lib/Digital%2074HCTxxx/ | 20:34 |
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