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| promach | Would it be nicer to use negative edge triggered 'reset' compared to its positive edge triggered counterparts ? | 02:32 |
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| ZirconiumX | Here's a probably quite cursed idea. | 18:04 |
| ZirconiumX | Yosys supports reading Verilog, optimising it, and writing it as BLIF | 18:04 |
| ZirconiumX | If you then use misII, which is a UCB tool from the 90's, you can read BLIF and turn it into 74-series logic | 18:05 |
| ZirconiumX | "But why?" | 18:05 |
| ZirconiumX | Good question | 18:06 |
| tnt | Why cursed ? I mean, if you need some logic done in 7400 that could be a totally valid way to find a solution possibly better than what you can come up with manually. | 18:08 |
| ZirconiumX | True, but it's a very hacky way of doing it | 18:09 |
| tnt | Maybe yosys has a 74 series mapping library natively ? | 18:09 |
| ZirconiumX | That's a question; how would you write one? | 18:14 |
| tnt | no clue | 18:15 |
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| ZipCPU | ZirconiumX: Check out the ABC pass. synch + abc can be used to map a design to a variety of simpler logic circuits, such as you might use with 74-series logic. It's not specific to it, but I think it should work | 19:11 |
| ZipCPU | "But why?" My son came home from college a semester ago with a requirement to design a particular 7-seg display circuit from straight logic gates. It's a whole lot easier to design and test in Verilog. Why no use Verilog, formally verify it, and then map it to gates using Yosys? | 19:12 |
| daveshah | ABC can natively map simple gates, for fancier gates you could write a Liberty file (like https://github.com/YosysHQ/yosys/blob/master/examples/cmos/cmos_cells.lib) to map to | 19:15 |
| tpb | Title: yosys/cmos_cells.lib at master · YosysHQ/yosys · GitHub (at github.com) | 19:15 |
| ZirconiumX | I want to experiment with designing and building a CPU out of 74-series logic | 19:15 |
| daveshah | But neither of these approaches support multiple-output gates, so you'd still be mapping gates rather than chips | 19:15 |
| daveshah | i.e. you won't get a minimum-chip solution | 19:15 |
| ZirconiumX | And, yeah, formal verification would be a bonus | 19:15 |
| ZirconiumX | daveshah: Maybe you could approximate it by tuning the area settings | 19:16 |
| daveshah | Yes, you could | 19:16 |
| ZirconiumX | For example you can fit two 4-input muxes in a 74153, but only one 8-input mux in a 74151 | 19:17 |
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| ZirconiumX | daveshah: So do I need to make an equivalent cell for AND/ANDNOT/whatever, or do I make my own cells and let ABC figure it out? | 19:32 |
| daveshah | ZirconiumX: I believe ABC needs three cells minimum: buffer, NOT and a logic gate (don't think the kind of gate matters much) | 19:34 |
| daveshah | Otherwise it won't be happy | 19:34 |
| ZirconiumX | Do they need to explicitly be named BUF/NOT/etc? | 19:38 |
| daveshah | No, only the function matters | 19:39 |
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| ZirconiumX | PicoRV32 apparently synthesizes to 398 7400 gates (so 99 ICs), and 93 7404 gates (so 16 ICs) | 19:49 |
| daveshah | That seems very low | 19:50 |
| daveshah | Maybe that isn't mapping the memory for some reason | 19:50 |
| daveshah | *register file | 19:50 |
| _vince | any comments on the chip stats? what's the most common chip in that circuit? | 19:50 |
| ZirconiumX | Since it only currently understands the 7400, 7404 and 74367, don't expect miracles | 19:51 |
| daveshah | The register file should need at least 1024 bits of state, so something must be going wrong | 19:51 |
| _vince | hand optimizing 74s is fun ZipCPU probably why they are making him do it | 19:51 |
| _vince | i had those kinds of exercises in high school electronics | 19:52 |
| _vince | definately a crude 7segment clock was a topic but with a lot of help - we didnt have to design everything | 19:52 |
| _vince | or was it that there was a 7s driver | 19:52 |
| _vince | with BCD input or something | 19:52 |
| ZirconiumX | Yeah, abc does not like multi-output gates | 19:55 |
| ZirconiumX | I got an assertion failure in Yosys | 19:55 |
| ZirconiumX | (why do I keep breaking this poor, poor program?) | 19:55 |
| ZirconiumX | daveshah: `hierarchy` appears to be pruning picorv32_regs? | 19:57 |
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| daveshah | I think picorv32_regs is an example of an external register file, picorv32 will use a built in one by default (set by a macro) | 19:59 |
| daveshah | So I doubt that is the problem | 19:59 |
| daveshah | You probably want `hierarchy -top picorv32; flatten` | 19:59 |
| ZirconiumX | Okay, that seems more reasonable | 20:00 |
| ZirconiumX | 3,722 7400 ICs, 579 7404 ICs, 6 74367 ICs | 20:02 |
| daveshah | I think you'll also need to map DFFs seperately - see `dfflibmap`, `abc` in this context will only map combinational logic | 20:03 |
| daveshah | That sounds about right | 20:03 |
| ZirconiumX | So presumably for DFF I need to include D flip-flops? | 20:05 |
| daveshah | Yes, and `dfflibmap` will map them seperately | 20:05 |
| ZirconiumX | Does it expect each flop to have its own clock? | 20:06 |
| daveshah | Yes - even though this isn't actually true for FPGA flows, usually this would be resolved in placement down the chain | 20:06 |
| ZirconiumX | Gonna be fun finding an equivalent chip then | 20:06 |
| daveshah | However, if there is only one clock in the design (as is the case with picorv32) then all flops will use that clock | 20:07 |
| daveshah | Yosys won't create clocks out of nowhere | 20:07 |
| ZirconiumX | There's the '574, but that only have one clock for 8 bits | 20:07 |
| daveshah | That will be fine | 20:07 |
| daveshah | I struggle to think of a design that has one clock domain for fewer than 8 bits... | 20:08 |
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| ZirconiumX | So after adding a '574, dfflibmap is still complaining about unmapped cells | 20:16 |
| ZirconiumX | DFFSR, which I think means a set-reset flip-flop? | 20:17 |
| ZirconiumX | And also things like $_DFF_NN0_ | 20:17 |
| ZirconiumX | daveshah: ^ | 20:17 |
| daveshah | Is this with picorv32? These would be DFFs with async set/resets | 20:18 |
| daveshah | Which I didn't think picorv32 had | 20:18 |
| ZirconiumX | Yes, it is | 20:18 |
| ZirconiumX | https://pastebin.com/R9K1eK35 | 20:19 |
| tpb | Title: 5. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty - Pastebin.com (at pastebin.com) | 20:19 |
| daveshah | Ah it's only saying it didn't find these cell types in the library | 20:19 |
| daveshah | But in this case it shouldn't need to map any of them | 20:19 |
| daveshah | You can check by running `stat` after `dfflibmap` | 20:20 |
| daveshah | This will show if there are any of these DFF types left unmapped | 20:20 |
| ZirconiumX | https://pastebin.com/Dh3Bw4FX | 20:20 |
| tpb | Title: 7. Printing statistics. === picorv32 === Number of wires: - Pastebin.com (at pastebin.com) | 20:20 |
| daveshah | Looks good, looks like it mapped all the DFFs | 20:22 |
| ZirconiumX | There is something quite amusing about this; using Yosys to design 1970's era logic | 20:25 |
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| ZirconiumX | https://pastebin.com/Nc5ibWdS | 21:00 |
| tpb | Title: 7. Printing statistics. === picorv32 === Number of wires: - Pastebin.com (at pastebin.com) | 21:01 |
| ZirconiumX | 7,583 cells | 21:01 |
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| ZirconiumX | I can synthesize VecRiscV too | 21:11 |
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| ZirconiumX | *VexRiscV | 21:11 |
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| ZirconiumX | ZipCPU: So it seems like formally verifying a CPU made out of 7400 logic might actually be possible | 21:19 |
| ZirconiumX | Although the "single output pin" problem is fairly crippling | 21:19 |
| ZirconiumX | Also dfflibmap does not like the idea of output-enable bits | 21:21 |
| ZipCPU | ;) | 21:39 |
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