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| tmbinc | Is there a plan to support SV's multi dimensional packed arrays? ("reg [3:0][3:0] data;") | 08:50 |
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| ZirconiumX | Where's the best place to post problems I'm having with Icarus Verilog, given that I'm a Verilog newbie and the error messages are awful? | 12:47 |
| ZirconiumX | Yosys accepts my code, Verilator accepts my code, but Icarus rejects it with a "malformed statement" error | 12:48 |
| tnt | ##openfpga ? | 12:50 |
| ZipCPU | Yeah, ##openfpga might be the best place | 13:08 |
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| corecode | ac | 13:57 |
| corecode | ops | 13:57 |
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