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| adamgreig | daveshah: i think commit https://github.com/YosysHQ/yosys/commit/ac6cc88db352938d8dd9f2f9c6d404663674538e has broken all my multi-clock bram inference on ice40 :p | 18:02 |
|---|---|---|
| tpb | Title: memory_bram: Fix multiclock make_transp · YosysHQ/yosys@ac6cc88 · GitHub (at github.com) | 18:02 |
| daveshah | adamgreig: it was always broken :p | 18:02 |
| daveshah | just not so visibly... | 18:02 |
| adamgreig | well before it worked and now it tries to use 65000 LCs instead of a few brams | 18:02 |
| adamgreig | so i guess i didn't notice the broken before but now it really is broken :P | 18:02 |
| daveshah | The iCE40 doesn't have a hardware transparent (write-through) BRAM mode | 18:03 |
| adamgreig | aha, that might be a good clue | 18:03 |
| daveshah | It is possible to fake this for a single clock domain, but afaik there is no guaranteed safe solution across clock domains to fake it | 18:03 |
| daveshah | Before Yosys tried, but this led to odd sim-synth mismatches | 18:04 |
| adamgreig | ack | 18:04 |
| adamgreig | I don't really care about write-through but I'm using nmigen and it might well be asking for that by default | 18:04 |
| daveshah | Hmm | 18:04 |
| daveshah | oMigen/LiteX definitely supports both | 18:04 |
| daveshah | I've seen both in its Verilog output | 18:05 |
| daveshah | not sure about nMigen, maybe it is an option? | 18:05 |
| adamgreig | it is an option on the read port | 18:05 |
| adamgreig | I'll see if that fixes things | 18:05 |
| adamgreig | yikes. it's certainly done something. | 18:10 |
| adamgreig | now I have hundreds fewer LCs and also no RAMs | 18:10 |
| tnt | adamgreig: what does the verilog look like | 18:16 |
| tnt | ? | 18:16 |
| adamgreig | nmigen generates RTLIL rather than verilog though I do have a minimal test case | 18:16 |
| adamgreig | however I think I've solved it now | 18:16 |
| adamgreig | I have to set transparent=True on the read port to allow yosys to infer it for ice40 | 18:17 |
| adamgreig | but then nmigen changes the read port enable from constant 1 to some undriven signal which resets to 0, so the read port was always disabled, which is why most of my design subsequently vanished | 18:17 |
| adamgreig | if I set transparent=False and assert rport.enable to 1 it all seems to work | 18:17 |
| adamgreig | so... user error I guess! albeit some slightly confusing api design | 18:18 |
| adamgreig | thanks daveshah! | 18:18 |
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