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| tnt | Any verilog semantics expert in the audience ? | 13:46 |
|---|---|---|
| tnt | https://github.com/m-labs/VexRiscv-verilog/issues/7 | 13:46 |
| tpb | Title: VexRiscv-Min variant misbheaving · Issue #7 · m-labs/VexRiscv-verilog · GitHub (at github.com) | 13:46 |
| tnt | Is the simulator wrong, or is this unspecified ... | 13:46 |
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| emeb | That's a tricky one. | 13:55 |
| tnt | if it was obvious, I wouldn't be asking :P | 13:56 |
| emeb | Of course! | 13:57 |
| emeb | Digging around in my copy of Thomas & Moorby doesn't give any good insight into this. | 14:20 |
| emeb | (Of course it's not the greatest reference on Verilog, but they did create the language...) | 14:21 |
| tnt | Yeah I tried reading the specs and ... I'm really not more informed than before either :p | 14:37 |
| emeb | I found a SNUG paper by Sutherland from long ago that looked like it might have some insight, but no... | 14:52 |
| emeb | http://www.sutherland-hdl.com/papers/2007-SNUG-SanJose_gotcha_again_paper.pdf | 14:52 |
| ZipCPU | I just looked through the issue and I'm struggling to understand the core of the issue | 14:55 |
| ZipCPU | Is there a statement misbehaving? Or a question of Verilog? | 14:55 |
| tnt | ZipCPU: If you look at the screenshot you'll see the _halt signal is '1'. But if you look at the verilog, you might expect it to be '0'. | 14:57 |
| tnt | And that's because in the verilog process it sets IBusSimplePlugin_cmd_valid to 0 after it was evaluated and caused IBusSimplePlugin_iBusRsp_stages_0_halt to be '1'. And iverilog apparently doesn't re-run that process after. | 14:58 |
| ZipCPU | Is that because cmd_valid and _halt are set in the same blcok? | 14:58 |
| tnt | yes. if you split them or if you set _valid at the beginning, it works as expected. | 14:58 |
| ZipCPU | So ... isn't that how simulation is supposed to work though? The blocking statements in the always block get executed in order, and you (the designer) are supposed to handle any dependencies | 14:59 |
| emeb | Probably a red herring, but I'm bothered by a combinatorial process that modifies a signal based on the state of that signal. Seems like that's ripe for zero-delay feedback problems. | 15:00 |
| tnt | that's the question ... | 15:00 |
| tnt | emeb: well valid doesn't depend on valid. | 15:00 |
| ZipCPU | I've seen several examples of what would otherwise be combinatorial processes placed together into one, and so declared as no longer feedback loops | 15:00 |
| ZipCPU | So, if you have two signals whose dependencies intertwine, and you place them within the sample always @(*) block, you (as the engineer) are supposed to deconflict the dependencies with the order of the statements | 15:01 |
| ZipCPU | The simulator trusts you (the engineer) to have sorted our the dependencies | 15:01 |
| emeb | tnt: oh - misread that then. | 15:02 |
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