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| dormando | is it possible to get nextpnr to visualize/outline wires specific to a module? | 04:17 |
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| tnt | dormando: not that I know. | 04:54 |
| tnt | you can select them one by one ... | 04:54 |
| dormando | heh. I did that for a few minutes. it's the one thing I miss from the ISE atrocity | 04:55 |
| tnt | Maybe a small python script could help. | 04:55 |
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| bluesceada | hey everyone, i want to NOT initialize BRAM in my ice40, to analyze the start up state of RAM, this is possible in lattice icecube2, but how would it be possible with yosys/nextpnr ? | 12:57 |
| bluesceada | i am already using the bare SB_RAM40_4K, but that alone doesn't help it | 12:57 |
| bluesceada | i tried withou specifying parameters, and I tried with giving all INIT parameters don't care's like: .INIT_0(256'hxxxx....xx) to .INIT_F(256'hxxx..xx) | 12:59 |
| bluesceada | in icecube2 we need to check a box in the tool to not initialize memories, while somewhere else they document to use the SB_RAM40_4K as a non-initialized memory ... but it soemhow is always reset to all-0's | 13:01 |
| bluesceada | (if we do not check the box, that is, otherwise it contains all seemingly random data) | 13:01 |
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| tnt | bluesceada: not sure it's supported | 13:15 |
| bluesceada | ok let's wait a bit if someone else shows up that might know | 13:16 |
| tnt | I'm looking at the icepack sources and I don't see anything that would disable it. | 13:20 |
| bluesceada | ah thanks for looking into it, you mean disabling the initialization? | 13:28 |
| bluesceada | seems yosys also goes with 'xxxx', so it must happen after yosys | 13:29 |
| bluesceada | so, probably the x will be replaced with 0 in some later step? | 13:29 |
| tnt | yeah, that's the very last step when converting the .asc into the .bin file ... | 13:29 |
| bluesceada | or rather, if there is no initialization, the packer will make it initialize to 0 | 13:29 |
| bluesceada | ok | 13:30 |
| tnt | so even if supported this wouldn't be in verilog, it would be an option during the icepack step. | 13:30 |
| bluesceada | ok that would also be fine of course | 13:30 |
| tnt | because as discussed recently you can't do that "per bram", it's per quadrant. | 13:30 |
| bluesceada | ok yes I think that is also how it's shown in icecube2 | 13:31 |
| tnt | you can try to comment out https://github.com/cliffordwolf/icestorm/blob/master/icepack/icepack.cc#L538 | 13:32 |
| tpb | Title: icestorm/icepack.cc at master · cliffordwolf/icestorm · GitHub (at github.com) | 13:32 |
| bluesceada | thanks | 13:33 |
| bluesceada | you think that complete if {..} ? | 13:34 |
| tnt | I'd try that yes | 13:43 |
| tnt | trying to make a PUF btw ? | 13:47 |
| bluesceada | tnt, yes, for the students in my lab | 13:48 |
| bluesceada | that used icecube2 before | 13:49 |
| bluesceada | btw it seems to work, partially | 13:50 |
| bluesceada | seems every second byte is still 00, but that might be another problem | 13:51 |
| bluesceada | from comparing the bitstream filesizes, it is now roughly on par with the icecube2-non-initialized one, but not exactly the same size | 14:01 |
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| bluesceada | ok got it, will try to make it a pull request for icepack soon... | 15:07 |
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| bluesceada | tnt, it was actually right what you said and I had another issue with word/byte addresses, however I also found that it is sufficient to exclude the last part of that if-condition in which BRAM is initialized | 15:07 |
| tnt | bluesceada: yeah, very possible you can comment less, but the rest of the commands written in that block wouldn't have any effect if you don't write any data, so they're useless. | 15:10 |
| tnt | but you could make the option allow to specify which bank # you want to include or not, maybe as a bitmask | 15:10 |
| bluesceada | ok i thought these might have to do with the mode of addressing, but yeah in the end it was wrong verilog | 15:11 |
| bluesceada | i dont have much time for this so I would just add a simple option ... | 15:12 |
| bluesceada | next thing we need later in the semester will be placement constraints, but i see this has been added to nextpnr :-) | 15:13 |
| bluesceada | so this lab will be completely on open source software :-) | 15:14 |
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| tnt | syntax is different than icecube for placement. (tbh I'm not even sure what the syntax was for icecube) | 15:15 |
| bluesceada | i think it is better, can work inline verilog code | 15:15 |
| bluesceada | more similar to how xilinx supports I think | 15:15 |
| bluesceada | but have to still take a closer look.. | 15:15 |
| tnt | Do you have an example howit was for icecube ? | 15:15 |
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| bluesceada | it needs to be inside the constraints file, not easy to handwrite imo, generated from the icecube gui | 15:19 |
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| bluesceada | if you want a full example, i can somehow make it accessible to you | 15:21 |
| tnt | nah it's fine, I was just curious | 15:22 |
| bluesceada | probably not too bad to support both ways | 15:22 |
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| bluesceada | for xilinx i was using a LOC constraint in a constraint file to place a full block. Then, within the block, relative location constraints (RLOC) as vhdl attributes (also works in verilog) | 15:24 |
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| mithro | Anyone know the best way to write a yosys pass that would propagate parameters following signal input / output cones? | 21:23 |
| mithro | daveshah: would this be something you could do with the new python API? | 21:28 |
| mithro | Anyone used the new Python API in Yosys? | 21:29 |
| daveshah | mithro: I haven't used the Python API yet, but this is the sort of thing it is designed for | 21:30 |
| mithro | daveshah: Is there any examples I might be able to crib from? | 21:31 |
| daveshah | mithro: https://github.com/YosysHQ/yosys/tree/master/examples/python-api | 21:31 |
| tpb | Title: yosys/examples/python-api at master · YosysHQ/yosys · GitHub (at github.com) | 21:31 |
| mithro | daveshah: Thanks! | 21:32 |
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