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| bwidawsk | ZipCPU› I actually have been trying with the lattice programmer, and no joy - which was why I wanted to try the open tools :-) | 01:23 |
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| ZipCPU | chaseemory: ;) | 02:34 |
| ZipCPU | bwidawsk: You mean the iCE40 1k stick? | 02:34 |
| * ZipCPU just finished showing 101 Dalmations to his kids | 02:35 | |
| * ZipCPU googles ECP5 evaluation board | 02:55 | |
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| bwidawsk | ZipCPU› no, the ECP5 EVN | 03:12 |
| * ZipCPU googles the ECP5 evaluation board | 03:12 | |
| ZipCPU | Looks like it has a QSPI flash on board, no? | 03:12 |
| bwidawsk | what's the 'Q'? | 03:12 |
| bwidawsk | mine has a macronix part | 03:13 |
| bwidawsk | 16pin SPI | 03:13 |
| ZipCPU | "Quad" SPI. It takes the MISO/MOSI/WP and HOLD pins and turns them all into bidirectional data | 03:13 |
| ZipCPU | Oh, 16pin SPI? | 03:13 |
| bwidawsk | well, spi is 1 pin, but the actual chip is 16 | 03:13 |
| * ZipCPU googles some more | 03:14 | |
| ZipCPU | Out of curiosity, what are your goals with the flash? Just initial startup configuration? | 03:15 |
| bwidawsk | oh, I didn't notice the special programming instructions | 03:15 |
| bwidawsk | http://www.latticesemi.com/view_document?document_id=52484 | 03:15 |
| bwidawsk | so at this point, I'm just trying to compare open vs. proprietary tools | 03:15 |
| ZipCPU | The data sheet I'm looking at, FPGA-EB-02017-1-0-ECCP5-Evaluation-Board.pdf shows a QSPI flash, with all the standard pins | 03:16 |
| bwidawsk | you have a link for that one handy? | 03:16 |
| ZipCPU | Sure, one moment | 03:17 |
| ZipCPU | I found it on this page: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard | 03:17 |
| tpb | Title: ECP5 Evaluation Board - Lattice Semiconductor (at www.latticesemi.com) | 03:17 |
| ZipCPU | I'm looking at the user guide, https://www.latticesemi.com/view_document?document_id=52479 | 03:17 |
| ZipCPU | ... and I'm on page 25 | 03:17 |
| bwidawsk | ZipCPU› hmm, maybe the other pins are grounded | 03:18 |
| ZipCPU | If you look at page 39, it shows a 16 pin flash, of which only 6 are used | 03:19 |
| ZipCPU | Some are grounded, some are test points | 03:19 |
| bwidawsk | yeah, okay, I hadn't dug that deeply | 03:19 |
| ZipCPU | I've written about how to build a QSPI flash controller that's highly configurable, yet very low logic | 03:19 |
| ZipCPU | The basic approach works nicely for dual SPI as well (strapped MISO+MOSI together for bidirectional data lines) | 03:20 |
| ZipCPU | While I have a regular SPI flash controller, it's not quite so configurable | 03:20 |
| bwidawsk | so... I was under the impression that I can program this flash with jtag, and then on subsequent boot, the bitstream would be loaded into the fpga? | 03:20 |
| ZipCPU | Yeah, that's usually how this sort of thing works. I usually load my design via JTAG, and the program the flash through the design, but I'm probably just strange that way | 03:21 |
| ZipCPU | *then program | 03:22 |
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| bwidawsk | well, if you know what you're doing, that's probably much faster | 03:50 |
| bwidawsk | I'm not sure if I need any straps, or something set to make it load from the SPI, but nothing seems to work for me | 03:51 |
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| bwidawsk | for whatever it's worth, I spent 3 days struggling with diamond and flexlm to get the blinky to work, and symbiflow/trellis worked within 30 seconds | 04:32 |
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