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| promach_ | For https://gist.github.com/promach/cf3ae626a85badad6cd822d3107c86b7#file-spidergon_router-v-L377 and https://i.imgur.com/5SAOEbF.png , why am I having "xxxxx" unknown signal ? | 05:59 |
|---|---|---|
| tpb | Title: Spidergon Networks On Chip ยท GitHub (at gist.github.com) | 05:59 |
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| ZipCPU | promach_t: Because you never initialized the signal | 10:24 |
| promach_ | ZipCPU: huh ? | 10:26 |
| promach_ | no | 10:26 |
| promach_ | see the other flit_data_output signals | 10:26 |
| promach_ | only flit_data_output<3> has unknown signal | 10:27 |
| ZipCPU | Wheres the initial statement giving it an initial value? | 10:28 |
| ZipCPU | I looked and didn't see it | 10:28 |
| promach_ | ZipCPU: I have added initial flit_data_output[port_num] = 0; , but same "xxxxx" unknown signals | 10:32 |
| ZipCPU | That's the problem. Keep working with it, and you should have it working | 10:35 |
| promach_ | ok, but I am not sure why the initial statement is not helping | 10:45 |
| ZipCPU | I'd have to see more details to know | 10:50 |
| * promach_ will leave this piece of verilog code until monday morning | 11:04 | |
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| promach_ | is there a way to make formal tool start BMC timestep 0 with a negedge instead of a posedge ? | 15:16 |
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| promach_ | ZipCPU: I think I found why... but it requires the formal tool to start with a negedge | 15:24 |
| promach_ | line 377 is for the reset | 15:26 |
| promach_ | and I have initial assume(reset); | 15:26 |
| promach_ | but then, initial flit_data_output[port_num] = 0; should have eliminated the "xxxxx" unknown signal .... :| | 15:35 |
| promach_ | I think I will just leave this until Monday .... | 15:36 |
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