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| bwidawsk | Is there anyone actively using yosys with intel/altera? | 20:48 |
|---|---|---|
| ZipCPU | I'm not sure about "actively", but what are you looking for? | 20:49 |
| ZipCPU | I've got one design that's close to being able to work with Yosys | 20:49 |
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| bwidawsk | ZipCPU: I'm just trying to understand a bit what's missing from the intel toolchain (I work for Intel and am a software dev just trying to figure out how things can be made better, if at all) | 22:35 |
| bwidawsk | like, if one wanted to not use quartus... | 22:36 |
| bwidawsk | I was surprised to see synth_intel was even available | 22:38 |
| bwidawsk | though I also don't quite grok the differences the underlying hardware makes at the netlist level | 22:38 |
| sorear | well if you tried to do synth_ecp5 you'd have a bad time because it would generate a netlist containing 4-LUTs and Lattice specific carry chain etc details | 22:40 |
| sorear | I don't think anyone who actively uses synth_intel is active on IRC; I haven't heard much about it one way or another | 22:40 |
| elms | bwidawsk: I haven't heard of any work on opening the steps after synthesis. So you would still need to use vendor tools for place and route and bitstream generation. | 23:01 |
| elms | bwidawsk: There is at least some recent contributions https://github.com/YosysHQ/yosys/issues/921 | 23:06 |
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| ZipCPU | bwidawsk: I have used synth_intel | 23:17 |
| ZipCPU | The path is to use synth_intel to create a vqm file, and then feed the vqm file to Quartus | 23:18 |
| ZipCPU | (There is no current open PNR for Intel devices) | 23:18 |
| ZipCPU | I have a project that is close to being ready, https://github.com/ZipCPU/arrowzip | 23:19 |
| tpb | Title: GitHub - ZipCPU/arrowzip: A ZipCPU based demonstration of the MAX1000 FPGA board (at github.com) | 23:19 |
| ZipCPU | The problem I've had working with it is that I need a variety of hardware specific modules: primarily ODDR and PLL | 23:19 |
| ZipCPU | These modules aren't well documented, if at all | 23:20 |
| ZipCPU | Specifically, you need to figure out how to use: fiftyfivenm_io_obuf fiftyfivenm_io_ibuf fiftyfivenm_ff fiftyfive_ddio_out and fiftyfivenm_pll | 23:21 |
| ZipCPU | I think I'm close, but got distracted before being able to push the design across the finish line | 23:21 |
| ZipCPU | (It currently works without Yosys, just not with) | 23:21 |
| bwidawsk | well, I'm still very much in the learning and exploratory stage, so mostly just trying to figure out what's missing and if it's something we should look into doing | 23:22 |
| bwidawsk | if there's nice easy ways to get started with contributing, I'd love to (I spent most of my career working on linux graphics drivers, so this is quite a departure) | 23:22 |
| ZipCPU | This work is nearly all software work | 23:22 |
| ZipCPU | At least .... to get this design to work, it'd be all software work | 23:23 |
| ZipCPU | The hardware involved is pretty inexpensive as well at $30 | 23:23 |
| bwidawsk | ZipCPU: so this is using quartus lite, I guess? | 23:24 |
| ZipCPU | Yes | 23:25 |
| bwidawsk | ZipCPU: okay, if you want to spend a few minutes giving a little write up of what needs doing, I can look. I'd like to get my feet wet with something tractable | 23:26 |
| bwidawsk | also, just curious are you programming the FPGA with the newish stuff that will land in linux 5.2? | 23:27 |
| bwidawsk | or using the closed drivers? | 23:27 |
| ZipCPU | This particular device I have programmed using libxsvf, since the Trenz drivers weren't working when I purchased my device | 23:28 |
| ZipCPU | So, here's the good news: all of the files Yosys works with are text files | 23:28 |
| ZipCPU | That includes the VQM file | 23:28 |
| ZipCPU | It's somewhat legible--there's no control codes, it's a file that describes structures, wires, and how they connect | 23:29 |
| ZipCPU | If you stare at it for a bit, you might get an idea | 23:29 |
| ZipCPU | However, my wife just got home from a week out of town, so ... if you'll excuse me, can I get back to you later? | 23:29 |
| bwidawsk | 👍 | 23:30 |
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