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| promach_ | corecode : do you think yosys-smtbmc is able to do NoC deadlock verification ? | 03:26 |
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| shorne | Hello, I am trying to synthesize mor1kx (an openrisc core) with yosys. I'm using the today's git version of yosys for the first time | 08:24 |
| shorne | just trying to run something like : yosys -f verilog -o synth.v -S mor1kx_dmmu.v mor1kx_true_dpram_sclk.v mor1kx_immu.v .... | 08:26 |
| shorne | after MEMEMORY_MAP phase I just get "Killed" | 08:27 |
| shorne | and it exits | 08:27 |
| shorne | something I am doing wrong? | 08:27 |
| tnt | Does 'dmesg' say anything ? | 08:30 |
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| daveshah | shorne: is it possible there are any large (e.g. tens to hundreds of MB) RAMs in there? | 09:29 |
| tnt | I would more suspect a RAM that ends up not being mapped to ... RAM. | 09:35 |
| daveshah | No RAMs will be mapped to RAM with -S which is generic logic synthesis | 09:37 |
| shorne | ok, maybe I am missing ram mapping | 09:37 |
| shorne | there might be around 1 MB or ram | 09:38 |
| shorne | We have caches and a ton of registers | 09:39 |
| shorne | but not that much | 09:39 |
| shorne | Running again | 09:39 |
| shorne | tnt: right its the oom killer | 09:39 |
| shorne | Out of memory: Kill process 21146 (yosys) score 614 or sacrifice child | 09:39 |
| tnt | 1 MB done in FF is ... a lot of FF and muxes and ... :p | 09:40 |
| shorne | ok, it worked after doing: yosys -f verilog -o synth.v -p memory -p opt -S mor1kx_dmmu.v ... | 09:43 |
| shorne | I was thinking the MEMORY_MAP was doing the memory conversions | 09:43 |
| shorne | Sorry, first time using yosys | 09:43 |
| shorne | recently I have just been using iverilog/verilator ... not synthesizing anything :) | 09:44 |
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| corecode | promach: how would you detect a deadlock? | 11:24 |
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| corecode | promach: what did you implement for your NoC so far? | 11:43 |
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| develonepi3 | andrewrk, updated zig ver c4887d7f. This is the cmd that I used to get zigmain.o zig build-obj -isystem ../../include/ -isystem /usr/lib/arm-none-eabi/include -isystem /usr/lib/arm-none-eabi -target armv7-freestanding-gnueabihf zigmain.zig. | 13:28 |
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| promach_ | corecode : if I use Spidergon, then I am afraid that I cannot avoid deadlock. I am not sure if I could combine Spidergon with turn-restriction routing | 14:50 |
| promach_ | I am not sure if I even want to detect | 14:51 |
| promach_ | when I could avoid/eliminate deadlock entirely | 14:51 |
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| corecode | why would you get a deadlock? | 15:48 |
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| FL4SHK | Does yosys have a VHDL frontend? | 18:48 |
| FL4SHK | also, regarding formal verification with yosys, is there any way to do so with VHDL? | 18:49 |
| FL4SHK | My guess and possibly correct "knowledge" is that neither of these are available. | 18:50 |
| FL4SHK | I thought I'd ask anyway, though. | 18:50 |
| tnt | There is a commercial 'plugin' I think. | 18:51 |
| daveshah | FL4SHK: There are some experimental projects to add VHDL frontends to Yosys, ime the best option is vhdl2vl | 18:51 |
| daveshah | The commercial frontend is Verific. This does support formal verification, at least asserts (not sure about assumes) | 18:51 |
| daveshah | If your purposes are research/personal/academic a free license might be available | 18:52 |
| daveshah | see https://www.symbioticeda.com/research-partner-license-program-serp/ and https://www.symbioticeda.com/education-and-training-seet-license-program/ | 18:52 |
| tpb | Title: Research Partner License Program (SERP) Symbiotic EDA (at www.symbioticeda.com) | 18:52 |
| FL4SHK | vhd2vl's existence actually surprises me | 18:52 |
| FL4SHK | wait | 18:54 |
| FL4SHK | doesn't support pcakages, structures, or functions? | 18:54 |
| FL4SHK | without those features, I have no need to use VHDL | 18:54 |
| tnt | :) | 18:54 |
| daveshah | No, vhdl2vl pretty much supports the verilog feature set only | 18:54 |
| FL4SHK | guess I'll continue with my compiler project then, heh. | 18:55 |
| FL4SHK | I'm not working on a VHDL compiler, but rather a compiler for a custom HDL | 18:55 |
| FL4SHK | it'll be spitting out Verilog-2001 | 18:55 |
| FL4SHK | the fact that it carries over comments is intriguing | 18:56 |
| FL4SHK | *the fact that vhd2vl | 18:56 |
| FL4SHK | I may or may not want to do so myself... | 18:57 |
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