| *** tpb has joined #yosys | 00:00 | |
| *** develonepi3 has quit IRC | 00:30 | |
| *** develonepi3 has joined #yosys | 00:34 | |
| *** gsi__ has joined #yosys | 01:46 | |
| *** gsi_ has quit IRC | 01:49 | |
| *** FL4SHK has quit IRC | 02:06 | |
| *** FL4SHK has joined #yosys | 02:17 | |
| *** proteusguy has quit IRC | 02:50 | |
| *** citypw has joined #yosys | 03:21 | |
| *** leviathanch has joined #yosys | 03:35 | |
| promach | corecode : is your usb verilog code posted in github repo ? | 04:06 |
|---|---|---|
| *** rohitksingh has quit IRC | 04:21 | |
| *** rohitksingh_work has joined #yosys | 04:44 | |
| *** pie___ has joined #yosys | 04:58 | |
| *** pie__ has quit IRC | 05:02 | |
| *** lutsabound has quit IRC | 05:13 | |
| *** emeb has quit IRC | 05:27 | |
| *** rohitksingh has joined #yosys | 06:05 | |
| jayaura | Hi, icebox_stat can list how many resources were used, but can some tool list whats the maximum available resources for the fpga the design was compiled for ? | 06:54 |
| *** ZipCPU has joined #yosys | 07:01 | |
| *** leviathanch has quit IRC | 08:00 | |
| *** m4ssi has joined #yosys | 08:17 | |
| *** rohitksingh has quit IRC | 09:08 | |
| *** rohitksingh has joined #yosys | 09:11 | |
| *** leviathanch has joined #yosys | 09:36 | |
| corecode | promach: i don't have usb verilog code | 10:12 |
| corecode | jayaura: you mean what the model has resources? | 10:12 |
| *** citypw has quit IRC | 10:13 | |
| jayaura | corecode: yes, like giving the resource summary as "GBUF: 8 of 8" instead of "GBUF: 8" as I see now | 10:14 |
| corecode | i guess you could modify the code | 10:14 |
| jayaura | I mentioned gbuf figuratively. | 10:15 |
| corecode | yes | 10:15 |
| jayaura | i mean, the toolchain already know what resouces the fpga part contains. why not just say it :P | 10:15 |
| corecode | because you didn't change the code yet | 10:15 |
| jayaura | is that necessary? when I do a clean build, shouldnt it report the used and available resources? | 10:16 |
| corecode | what do you mean by clean build | 10:17 |
| daveshah | Both arachne-pnr and nextpnr will print both resource usage and total available during pnr | 10:23 |
| jayaura | Ah sorry my mistake. I needed to look inbetween. I was looking at the end. arachne-pnr was only reporting span4 and span12 at the end, and not the LCs statistics, which was summarized right after placement | 10:57 |
| promach | corecode : wait, I thought you said coded something on usb ? | 11:03 |
| corecode | yes, for microcontrollers | 11:05 |
| promach | so, the code is not in verilog ? | 11:05 |
| promach | corecode | 11:05 |
| corecode | no, it's code, not design | 11:10 |
| promach | corecode : I do not get you | 11:17 |
| promach | I remembered you said you coded something on usb ? | 11:18 |
| promach | "it's code, not design" ?? | 11:18 |
| *** proteusguy has joined #yosys | 11:37 | |
| *** massi_ has joined #yosys | 11:51 | |
| corecode | yes, code | 12:07 |
| corecode | for a microcontroller | 12:08 |
| corecode | no hdl | 12:08 |
| promach | c ? | 12:08 |
| corecode | yes | 12:08 |
| promach | I really do not want to deal with the usb linux driver c code | 12:09 |
| promach | that is so ugly to debug if you really need to (which I think is bug-free) | 12:09 |
| promach | corecode | 12:09 |
| corecode | what is bug free? | 12:09 |
| promach | free of bugs | 12:09 |
| corecode | what is bug free | 12:09 |
| promach | like receiving the wrong data from the usb protocol | 12:10 |
| promach | which is impossible at all | 12:10 |
| promach | given that usb had evolved so far | 12:10 |
| corecode | what are you talking about | 12:10 |
| promach | corecode | 12:10 |
| promach | I am talking about libusb | 12:10 |
| promach | https://github.com/libusb/libusb/wiki | 12:11 |
| tpb | Title: Home · libusb/libusb Wiki · GitHub (at github.com) | 12:11 |
| promach | c code is much more difficult to debug compared to verilog code | 12:11 |
| promach | I might be wrong, but it is just personal experience | 12:12 |
| promach | corecode | 12:12 |
| *** m4ssi has quit IRC | 12:25 | |
| *** rohitksingh_work has quit IRC | 13:00 | |
| *** rohitksingh has quit IRC | 13:03 | |
| *** rohitksingh has joined #yosys | 13:49 | |
| MoeIcenowy | icebox_vlog cannot deal with UP IP? | 14:40 |
| MoeIcenowy | I tried to use it to generate a verilog for UPduino RGB blink sample | 14:40 |
| MoeIcenowy | and I found no IP is generated | 14:40 |
| daveshah | No, it can't | 14:41 |
| MoeIcenowy | daveshah: I found that the verilog file of the sample defines LED pins as output | 14:43 |
| MoeIcenowy | will the same be needed for yosys-nextpnr workflow? | 14:43 |
| daveshah | No, just the driver primitive should be fine | 14:43 |
| *** kraiskil has joined #yosys | 14:55 | |
| *** citypw has joined #yosys | 14:56 | |
| *** emeb has joined #yosys | 15:01 | |
| MoeIcenowy | daveshah: a module without any input or output, but only IPs will not be "optimized"? | 15:01 |
| corecode | wa? | 15:01 |
| corecode | what kind of module would that be? | 15:02 |
| corecode | no input or output | 15:02 |
| MoeIcenowy | calls HFOSC | 15:02 |
| MoeIcenowy | then RGBDRV | 15:02 |
| corecode | calls? | 15:02 |
| daveshah | Just double checked and keep isn't set on the RGB primitive, so it does need outputs actually | 15:02 |
| daveshah | Adding `(* keep *)` here would change that if you wan it: https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v#L944 | 15:02 |
| tpb | Title: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at github.com) | 15:02 |
| MoeIcenowy | but I think I will choose to use the oscillator on board with my own board ;-) | 15:09 |
| MoeIcenowy | just borrow a bitstream from UPduino now to test | 15:09 |
| MoeIcenowy | my iCE40UP5K-SG48I's arrived LCSC at Shenzhen today | 15:09 |
| MoeIcenowy | and will ship to me tomorrow | 15:09 |
| tnt | oh they have ice40s now ? | 15:33 |
| *** kraiskil has quit IRC | 15:43 | |
| corecode | MoeIcenowy: where are you at? | 15:49 |
| MoeIcenowy | tnt: no, it's digikey via LCSC ;-) | 15:51 |
| MoeIcenowy | corecode: Guangzhou | 15:52 |
| corecode | ah, close to sz | 15:52 |
| corecode | or? | 15:52 |
| MoeIcenowy | yes, close to sz | 15:52 |
| MoeIcenowy | 1 hrs of high-speed train | 15:52 |
| MoeIcenowy | s/hrs/hr/ | 15:52 |
| corecode | did you move there or were you born there? | 15:53 |
| tnt | MoeIcenowy: oh they do that ? didn't know | 15:54 |
| MoeIcenowy | corecode: moved here 9 yrs ago | 15:56 |
| MoeIcenowy | tnt: only available at China | 15:56 |
| corecode | do you like it? | 15:56 |
| MoeIcenowy | strangely the components at Digikey via LCSC is (very) slightly cheaper than Digikey itself | 15:57 |
| corecode | maybe special contract | 15:57 |
| MoeIcenowy | for example, the price of iCE40UP5K-SG48I on Digikey itself is CNY 49 | 15:58 |
| MoeIcenowy | but on Digikey via LCSC it's 47 | 15:58 |
| MoeIcenowy | and Digikey itself requires one order must be at least CNY300 | 15:58 |
| MoeIcenowy | but Digikey via LCSC has no restriction | 15:58 |
| MoeIcenowy | (yes, my order is only 5 iCE40UP5K-SG48I's, so it's less than 300 | 15:59 |
| corecode | i guess they pool orders | 16:01 |
| *** rohitksingh has quit IRC | 16:07 | |
| *** rohitksingh has joined #yosys | 16:14 | |
| *** ec0 has quit IRC | 16:25 | |
| *** ec0 has joined #yosys | 16:27 | |
| *** maikmerten has joined #yosys | 16:33 | |
| *** kraiskil has joined #yosys | 16:41 | |
| *** leviathanch has quit IRC | 16:48 | |
| *** citypw has quit IRC | 17:00 | |
| *** X-Scale has quit IRC | 17:41 | |
| *** X-Scale` has joined #yosys | 17:42 | |
| *** massi_ has quit IRC | 18:41 | |
| emeb | corecode: yay - got my old u4k breakout board blinking w/ your icestorm work. Thanks for getting that going. | 18:51 |
| *** lutsabound has joined #yosys | 19:07 | |
| corecode | cool | 19:08 |
| emeb | corecode: do you have any idea how much effort it would be to add support for the LED driver core in u4k? Without that those three pins appear to be unusable. | 19:16 |
| corecode | you can put ios on there | 19:17 |
| corecode | but they are OD | 19:17 |
| emeb | corecode: Ah ok - I'll give that a shot. | 19:17 |
| emeb | OD is fine for driving LEDs - just don't get the current control I guess. | 19:17 |
| corecode | yes | 19:17 |
| emeb | seems to work fine. thx. | 19:21 |
| corecode | cool | 19:22 |
| *** rohitksingh has quit IRC | 19:23 | |
| emeb | so I guess it's just that the proper hooks for those IP cores isn't in nextpnr at the moment? | 19:23 |
| corecode | no | 19:24 |
| corecode | the cores for the u4k are a bit different | 19:24 |
| emeb | ah, so it would be necessary to RE them and add support to yosys too. | 19:25 |
| corecode | yes, most of the work will be in icestorm | 19:25 |
| emeb | ok, probably not really worth it just to save a few resistors. :) | 19:26 |
| emeb | corecode: is there anyplace I can look to see exactly what features of u4k are unsupported, or is it just a "try and find out" problem? | 19:28 |
| corecode | yes, look in icebox.py at the list of peripherals | 19:29 |
| ylamarre | Documentation is in the code! :D | 19:29 |
| ylamarre | Ah! :P | 19:29 |
| corecode | the u4k ones are really short compared to the 5k | 19:29 |
| corecode | so those can be reversed and/or confirmed | 19:30 |
| emeb | corecode: thanks - I'll take a look. | 19:30 |
| emeb | (don't know the ice* codebase well enough to know where everything is) | 19:30 |
| daveshah | emeb: The resource utilisation print of nextpnr is also a good list of what primitives are available | 19:31 |
| daveshah | although, of course, it doesn't tell you which will actually work | 19:31 |
| * ylamarre was actually joking. | 19:31 | |
| ylamarre | But turns out, code IS the doc in this case... | 19:32 |
| emeb | daveshah: cool | 19:32 |
| emeb | ylamarre: I figured you were actually right. | 19:32 |
| emeb | the resource util pg for my blinky design: https://pastebin.com/9BRQpEbR | 19:33 |
| tpb | Title: Info: Device utilisation: Info: ICESTORM_LC: 28/ 3520 0% Info - Pastebin.com (at pastebin.com) | 19:33 |
| ylamarre | emeb: From what I remember icebox.py is quite nice to go through. Not too difficult to read last time I checked. | 19:33 |
| emeb | so looks like all the stuff I care about is there. | 19:34 |
| ylamarre | But that was like 3 years ago when there was only support for ice40LP/HX | 19:34 |
| emeb | looking at it now - it's a big file but not hard to navigate. | 19:35 |
| emeb | heh - u4k extra bits db "made up" - I guess that means they don't actually work. | 19:39 |
| corecode | yea i didn't bother with trying them for a different footprint | 19:45 |
| emeb | heh, yeah. the other footprints are not super easy to design with. | 19:48 |
| emeb | I've got one of the "official" Lattice breakouts for the u4k and it's got the little WLCSP-36 part. Hard to imagine the kind of PCB rules you'd need to use that. | 19:51 |
| corecode | yey so you can port for that footprint | 20:04 |
| emeb | lol yes - if I knew WTF I was doing. :) | 20:05 |
| corecode | yea that's how i started | 20:05 |
| emeb | I know that clifford wrote up some #exactsteps for the the process of adding stuff a few years back. I wonder if those still apply. | 20:07 |
| *** ZipCPU has quit IRC | 20:09 | |
| *** ZipCPU has joined #yosys | 20:13 | |
| *** kraiskil has quit IRC | 20:42 | |
| corecode | so if you just want to map out connections, just instantiate the IP core and look at the explain output | 20:56 |
| *** m4ssi has joined #yosys | 21:05 | |
| *** lutsabound has quit IRC | 21:27 | |
| *** lutsabound has joined #yosys | 21:30 | |
| *** maikmerten has quit IRC | 21:35 | |
| *** jwhitmore has joined #yosys | 21:38 | |
| *** gsi__ is now known as gsi_ | 21:56 | |
| emeb | corecode: for the n00b, which tool generates explain? | 22:03 |
| emeb | derp - icebox_explain. :P | 22:12 |
| *** jwhitmore has quit IRC | 22:16 | |
| corecode | :D | 22:29 |
| emeb | is it my imagination or are the cell coords given by explain off-by-one from those displayed in the icecube floorplanner? | 22:54 |
| emeb | nah - they're fine. | 22:56 |
| *** m4ssi has quit IRC | 23:41 | |
| *** lutsabound has quit IRC | 23:57 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!