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| MoeIcenowy | how much current will an iCE40UP5K cost at most? | 13:48 |
|---|---|---|
| tnt | like 10-20 mA 1.2v core current at the _very_ most. | 13:52 |
| tnt | for the IO ... well, that's mostly whatever you connect on those IO. | 13:53 |
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| tnt | I have no idea if it's even doable, but I wish there was a way to tell yosys to not create a different control set (i.e. Clk / CE / Set/Reset) for the bits of a same vector create from the same verilog statement. | 15:13 |
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| tnt | It's virtually never what I want. | 15:13 |
| tnt | "Great you saved 1 LUT4 by using the Set/Reset ... but (1) it's not really saved because the LUT4 is there anyway and has to be used as pass through (2) now the entire PLB is used up by 1 LC because that controlset is not used anywhere else" | 15:15 |
| corecode | \o/ the bin works! | 16:15 |
| corecode | blinks | 16:15 |
| daveshah | \o/ | 16:16 |
| corecode | finally i can unrecurse my yak | 16:16 |
| corecode | and get on with my cpu design | 16:17 |
| daveshah | :D | 16:17 |
| corecode | tnt: what would you like to see instead? | 16:17 |
| corecode | daveshah: is there anything else i need to do for these PRs, or do we just wait until somebody commits? | 16:33 |
| daveshah | I'll get clifford to review the icestorm one, then merge the nextpnr one once that's done | 16:34 |
| corecode | cool | 16:34 |
| tnt | corecode: well instead of using the 'set' line, it could pack an OR in the LUT4 before the FF. | 16:35 |
| corecode | aha | 16:36 |
| corecode | if it is a sync set | 16:36 |
| tnt | it is. | 16:36 |
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| tnt | And in another instance, for some reason, it decided to use the CE line instead of a MUX with previous value for a _single_ bit of a 12 bit vector ... (even though it doesn't save anything, the LUT4 before that FF could be used for that with no overhead). | 16:37 |
| corecode | isn't that a thing the placer also needs to have a say in? | 16:37 |
| tnt | the synth does the LUT packing, so it should know that this fits inside the LUT preceding the FF. | 16:38 |
| daveshah | It wouldn't be a big pass to unpack CE/SR if (a) the FF is driven by a LUT with spare inputs or (b) the FF is driven by a non-LUT or LUT with fanout >1 | 16:39 |
| daveshah | not that I have time to write it any time soon | 16:39 |
| corecode | why fanout>1? | 16:40 |
| daveshah | somewhat arbitrarily we separate the FF from the LUT in these cases rather than duplicating the LUT | 16:41 |
| daveshah | probably slightly reduces routing congestion, as only one signal to route rather than 1-4 | 16:41 |
| corecode | ah, the DFF can only receive input from the LUT out? | 16:41 |
| daveshah | yeah | 16:42 |
| daveshah | unlike most other FPGA arches | 16:42 |
| corecode | i see | 16:42 |
| corecode | who inserts the passthrough LUT? | 16:42 |
| daveshah | nextpnr | 16:42 |
| corecode | but if you wrote a pass to check for LUT out > 1, you might as well do it in yosys? | 16:42 |
| daveshah | corecode: icestorm PR is merged | 16:43 |
| daveshah | can you update https://github.com/YosysHQ/nextpnr/blob/master/.cirrus/Dockerfile.ubuntu16.04#L30 in your branch so that nextpnr CI should pass? | 16:44 |
| tpb | Title: nextpnr/Dockerfile.ubuntu16.04 at master · YosysHQ/nextpnr · GitHub (at github.com) | 16:44 |
| tnt | daveshah: thing is, I'd mostly like that decision to be based on the full vector rather than individual bits, to avoid creating different control sets. | 16:44 |
| corecode | will do | 16:44 |
| corecode | tnt: because of timing? | 16:51 |
| tnt | corecode: because I don't want to waste PLBs | 16:52 |
| corecode | for a vector you have the advantage of sharing the signals tho | 16:52 |
| tnt | corecode: LCs with different control set can't be packed in the same PLB. | 16:52 |
| corecode | yes | 16:52 |
| MoeIcenowy | daveshah: how to estimate how much power will iCE40 drain? | 16:53 |
| daveshah | I think Lattice have a tool somewhere | 16:53 |
| MoeIcenowy | I'm considering to make a board with small-size LDO | 16:53 |
| daveshah | the answer is not much :) | 16:53 |
| MoeIcenowy | daveshah: is there an upper bonud | 16:53 |
| MoeIcenowy | bound * | 16:53 |
| daveshah | for the up5k? 30mA | 16:53 |
| MoeIcenowy | the datasheet says booting peak current | 16:53 |
| MoeIcenowy | but no highest operation current | 16:54 |
| daveshah | no, that's quite hard to specify | 16:54 |
| MoeIcenowy | maybe I should download the design checklist by Lattice? | 16:54 |
| tnt | MoeIcenowy: the icebreaker uses sot-23 linear regulators. | 16:55 |
| daveshah | fwiw, MARLANN (simple CNN accelerator) using all DSPs, SPRAM and majority of LUTs at 20MHz consumes 14mA Vcore | 16:56 |
| daveshah | going above 40MHz for a large design would be very hard, so that would give about 30mA max | 16:56 |
| corecode | MoeIcenowy: yea, also understand difference between core and IO current | 16:59 |
| MoeIcenowy | tnt: okay ;-) | 16:59 |
| MoeIcenowy | seems that 200mA is enough? | 16:59 |
| corecode | for what rail | 17:00 |
| daveshah | If it draws 200mA Vcore it is probably dead :P | 17:00 |
| daveshah | IO pins are 8mA nominal max current, so max for all 36 non-open-drain pins is 288mA, but that's quite a crazy case | 17:00 |
| corecode | i use a mic5504-1.2 fwiw | 17:01 |
| tnt | daveshah: or like me you soldered it 90deg off :p | 17:01 |
| corecode | daveshah: yea but isn't switching current higher? | 17:01 |
| daveshah | corecode: maybe a bit, probably not that significant at iCE40 freqs and slew rates though | 17:01 |
| corecode | ok | 17:02 |
| corecode | well, knowing the application + math = success | 17:02 |
| MoeIcenowy | tnt: is your chip still alive? | 17:02 |
| MoeIcenowy | or does it rest in peace? | 17:02 |
| tnt | MoeIcenowy: it survived just fine :) | 17:03 |
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| corecode | imaginary current | 17:08 |
| MoeIcenowy | oh as a Computer Science student I know none about imaginary in circuits | 17:19 |
| corecode | it's a joke | 17:20 |
| corecode | because the chip was 90 degree offset | 17:20 |
| shapr | zing | 17:26 |
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| corecode | hm, syntax error | 21:16 |
| corecode | top.v:39: ERROR: syntax error, unexpected ATTR_END, expecting TOK_ID | 21:17 |
| corecode | i can't use catch all signal assignments? | 21:17 |
| daveshah | sounds like systemverilog | 21:17 |
| daveshah | what does your code look like? | 21:17 |
| corecode | module instantiation with , .*); | 21:18 |
| corecode | hm i guess everybody else accepted it | 21:18 |
| daveshah | yeah, that's valid systemverilog only | 21:18 |
| corecode | even with -sv yosys doesn't like it | 21:19 |
| corecode | sadface | 21:19 |
| daveshah | no, yosys only has limited sv support right now | 21:20 |
| corecode | i wonder whether some emacs autoparam magic will do the right thing | 21:20 |
| corecode | a: yes. | 21:22 |
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| corecode | somehow i can't get verilog-mode to align my hand written ports in an instantiation | 21:54 |
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| corecode | so what's the suggested way to design a POR | 23:18 |
| corecode | nothing? | 23:18 |
| ZipCPU | reg por; initial por = 1'b1; always @(posedge i_clk) por <= 1'b0; | 23:21 |
| corecode | ah, synchronous | 23:22 |
| corecode | yea i had something like that, just more complicated with multiple shifts | 23:22 |
| corecode | hm, now only 28MHZ? | 23:30 |
| corecode | so how come icecube says clock frequency 47MHz | 23:37 |
| corecode | and nextpnr says 28MHz | 23:37 |
| corecode | but then, icecube can't place my ram, so... | 23:37 |
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| corecode | how do i read this slack histogram? | 23:44 |
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