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| chaseemory | ZipCPU, i managed to get the Ethernet port working on the Nexys Video, it was a mixture of a few issues, wireshark came in super handy | 01:25 |
|---|---|---|
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| ZipCPU | Yaaayyy!!! | 01:32 |
| ZipCPU | chaseemory: Can you tell me what you used for the clock on the transmitter? | 01:32 |
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| chaseemory | i made two 125MHz clocks in an mmcm, one 90degrees out of phase, i dug through the layers of the code in the repo and thats the clock it seems to be using for the tx_clk | 01:46 |
| chaseemory | ZipCPU: https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/rgmii_phy_if.v | 01:48 |
| tpb | Title: verilog-ethernet/rgmii_phy_if.v at master · alexforencich/verilog-ethernet · GitHub (at github.com) | 01:48 |
| ZipCPU | Thanks! I'll take a peek | 01:48 |
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| mithro | ZipCPU: You should tell chaseemory about liteeth - it already supports GigE on Nexys Video plus a bunch of other stuff too | 05:45 |
| mithro | ZipCPU: _florent_ was getting liteeth working on the ECP5 too | 05:45 |
| MoeIcenowy | bought an EP4CE115 board with DDR2 SO-DIMM connector | 06:12 |
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| MoeIcenowy | seems that utilizing DDR memory is a disaster... | 06:13 |
| MoeIcenowy | (I do not like vendor IP | 06:13 |
| sorear | actually having a DIMM connector is good | 06:13 |
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| MoeIcenowy | sorear: yes, it's easily replaceable memory ;-) | 09:48 |
| MoeIcenowy | I love the connector | 09:48 |
| MoeIcenowy | but I don't love to utilize DDR on FPGA | 09:48 |
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| corecode | daveshah: ok, i think the last thing is to fill the extra_cells_db | 10:27 |
| daveshah | corecode: yeah | 10:29 |
| daveshah | for SB_WARMBOOT, create one and trace the routing in icebox_vlog | 10:29 |
| daveshah | for the remaining IP, hopefully the script for the UltraPlus is adaptable | 10:29 |
| corecode | warmboot i already handled | 10:30 |
| corecode | well, i'll skip the i2c and spi for now | 10:31 |
| corecode | but hfosc and lfosc is important | 10:31 |
| corecode | i guess there is no test fixture for it yet | 10:33 |
| corecode | what's the easiest way to figure out where config bits sit? | 10:34 |
| corecode | set them and look in the explanation? | 10:34 |
| MoeIcenowy | oh my laptop's LCD screen is too small in points to use the DDR2 controller IP from Quartus ;-) | 10:38 |
| corecode | daveshah: do i have to modify the standard cell library to access the TRIM input? | 10:53 |
| corecode | huh, icecube says "no top-level module" | 11:13 |
| corecode | what's that about | 11:13 |
| corecode | ah! | 11:14 |
| corecode | found it | 11:14 |
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| corecode | daveshah: trying to find the extra_cells for the hfosc - how do i know the location of the CLKHF output? i used it for a SB_IO output clock, but vlog says: | 11:31 |
| corecode | wire io_19_31_0; | 11:31 |
| corecode | // (0, 0, 'glb_netwk_4') | 11:31 |
| corecode | // (9, 31, 'io_global/outclk') | 11:31 |
| corecode | // (19, 31, 'io_0/PAD') | 11:31 |
| corecode | // (19, 31, 'padin_0') | 11:31 |
| corecode | is (0, 0) credible there? | 11:31 |
| daveshah | yes, it is global network glb_netwk_4 | 11:31 |
| daveshah | routed through the padin of 19, 31 | 11:31 |
| corecode | because on the 5k it is (0, 29) | 11:32 |
| daveshah | the global networks are really in every tile, so it doesn't matter | 11:32 |
| corecode | aha | 11:32 |
| daveshah | it's the glb_netwk_4 that's important | 11:32 |
| corecode | hm, why doesn't vlog show the HFOSC | 11:33 |
| daveshah | it doesn't support them | 11:33 |
| corecode | aha :) | 11:33 |
| corecode | hm, i thought HFOSC was global network 5 according to docs | 11:44 |
| daveshah | wouldn't be the first mistake in Lattice docs | 11:48 |
| daveshah | it's glb_netwk_4 on the up5k too | 11:49 |
| corecode | is that different from some other global buffer stuff? | 11:49 |
| daveshah | no | 11:49 |
| daveshah | the only difference is the SB_GB driving a different glb_netwk_i to the SB_GB_IO/padin at the same location | 11:50 |
| corecode | now i question my padin_io and padin_glb_netwk | 11:50 |
| corecode | so the HFOSC is global network 4, but routed via padin_glb_netwk 5? | 11:55 |
| corecode | oO | 11:55 |
| daveshah | no | 11:55 |
| corecode | or is that output of icebox_explain just what i did | 11:55 |
| daveshah | the HFOSC is global network 4 plain and simple | 11:55 |
| daveshah | this is entirely padin | 11:55 |
| corecode | ok, so i need to switch those two around | 11:57 |
| daveshah | which two? | 11:57 |
| corecode | HF and LF padin | 11:57 |
| daveshah | yeah | 11:58 |
| corecode | ok i need to redo my gbufin | 11:59 |
| corecode | i had some bogus data on it which confused me | 12:00 |
| daveshah | the important thing gbufin is totally unrelated to padin | 12:00 |
| daveshah | it's just coincidental that the locations are the same | 12:00 |
| corecode | especially if i cannot trust the ice docs | 12:00 |
| corecode | which means my explain output is unreliable as well | 12:00 |
| daveshah | no, the explain output will always be correct | 12:01 |
| daveshah | it doesn't rely on gbufin or padin at all | 12:01 |
| corecode | for the extra bits it uses the extra bit info | 12:01 |
| corecode | which was wrong for me | 12:01 |
| daveshah | ah, right | 12:01 |
| daveshah | inside logic, IO tiles, etc the glb_netwk_* will always be correct though | 12:01 |
| corecode | ok | 12:02 |
| daveshah | they are based on the low level routing bits determined by icefuzz and the glb files | 12:02 |
| corecode | ok, i'm looking at gbufin right now | 12:03 |
| corecode | i have clk on pin 44 | 12:03 |
| corecode | which the docs say is G6 | 12:03 |
| daveshah | The global numbers for the docs are for padin | 12:03 |
| daveshah | not gbufin | 12:03 |
| corecode | what? how would that be useful | 12:04 |
| daveshah | i.e. the global numbers in the docs (if they are correct) will only apply if using SB_GB_IO | 12:04 |
| daveshah | SB_GB are driven from fabric rather than an IO pin | 12:04 |
| corecode | yes, i thought gbufin is from the outside | 12:04 |
| daveshah | no, gbufin is for SB_GBs from fabric | 12:04 |
| corecode | god damn, these names are so confusing | 12:04 |
| daveshah | padin is for SB_GB_IOs from the IO pins | 12:04 |
| corecode | alright, back to padin | 12:05 |
| daveshah | beware that connecting to a SB_GB to a pin doesn't guarantee that icecube will place that GB next to the pin (unlike an SB_GB_IO) | 12:05 |
| corecode | so i have a sb_gb_io, and explain says it uses glb_netwk_1 | 12:05 |
| daveshah | yeah | 12:06 |
| corecode | but the docs say it is G6 | 12:06 |
| daveshah | this is inside a logic/io tile and not extra bits? | 12:06 |
| corecode | it also sets extra bits | 12:06 |
| daveshah | ignore the extra bits for now, just look at the routing in logic/io tiles | 12:06 |
| corecode | should i use explain or vlog? | 12:07 |
| daveshah | explain | 12:07 |
| daveshah | also, extra bitS or just one extra bit? | 12:07 |
| corecode | one | 12:07 |
| daveshah | good | 12:07 |
| daveshah | can you post the explain output? | 12:07 |
| corecode | buffer glb_netwk_1 io_global/outclk | 12:07 |
| corecode | sure | 12:07 |
| corecode | https://gist.github.com/c528fb3c6f3ceea2323ea190f34e3fe7 | 12:08 |
| tpb | Title: glb_u4k_pin_44.tcl · GitHub (at gist.github.com) | 12:08 |
| daveshah | so that is driving glb_netwk_1 for sure (and it looks like your extra bits database is wrong) | 12:09 |
| corecode | yes | 12:09 |
| daveshah | that is coming from IO (6, 0, 1)? | 12:09 |
| daveshah | IO (6, 0, 1) also drives glb_netwk_1 on the up5k | 12:10 |
| corecode | where do you get (6, 0, 1) from? | 12:11 |
| daveshah | IE_0 in io_tile 6, 0 | 12:11 |
| daveshah | IE_0 corresponds to pin z 1 because of the swapped ierens | 12:11 |
| corecode | aaaaaaa | 12:12 |
| corecode | they're swapped on one side? | 12:12 |
| daveshah | both sides according to your ieren db | 12:13 |
| daveshah | which also matches the ultraplus | 12:13 |
| daveshah | this only applies to the IE/REN bits in icebox_explain | 12:14 |
| corecode | aha | 12:14 |
| daveshah | everywhere else should use the normal, unswapped values | 12:14 |
| daveshah | looking at the Lattice docs, I think Lattice themselves were confused between gbufin/padin | 12:14 |
| daveshah | The UltraPlus docs and pinout by Lattice give padin numbers for IO, which makes sense | 12:14 |
| daveshah | it looks like some of the Ultra docs give gbufin numbers for locations | 12:15 |
| corecode | okay, so i corrected the 4 pins i have | 12:17 |
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| corecode | daveshah: i guess for the timing generation i first need yosys to work with the part? | 15:40 |
| corecode | https://github.com/cliffordwolf/icestorm/pull/202 | 15:41 |
| tpb | Title: iCE40 Ultra = iCE5LP = u4k port by corecode · Pull Request #202 · cliffordwolf/icestorm · GitHub (at github.com) | 15:41 |
| * sxpert uses alien on diamond's rpm... | 15:45 | |
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| MoeIcenowy | sxpert: sigh | 15:50 |
| MoeIcenowy | is Diamond only available in RPM? | 15:50 |
| corecode | what else | 15:50 |
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| sxpert | MoeIcenowy: yeah | 15:51 |
| sxpert | "for redhat enterprise linux blah" | 15:51 |
| sxpert | and then you have the stupid licensing stuff which I have yet to figure out | 15:52 |
| corecode | i somehow had to create an alias for eth0 | 15:52 |
| MoeIcenowy | I disabled the NIC renaming to run iCEcube2 | 15:52 |
| corecode | ah that's what it was | 15:52 |
| sxpert | oh, and they can't seem to be bothered to roll all their patches in one single file, you have to install a separate sp3 package... sigh | 15:52 |
| sxpert | corecode: does it REQUIRES an eth0 ? | 15:53 |
| sxpert | or do you need something else ? | 15:53 |
| corecode | that | 15:53 |
| corecode | and it might have been icecube | 15:53 |
| sxpert | ah, ok, all set then | 15:54 |
| sxpert | obviously, you could just popup a virtual eth card with a bogus mac | 15:54 |
| somlo | or, even better, "tunctl -t eth0" | 15:55 |
| somlo | it'll be there, but do nothing (other than shut up Vivado or Diamond or whatever is looking for it ) :) | 15:55 |
| sxpert | heh yeah | 15:56 |
| daveshah | corecode: The changes to Yosys will be minimal | 15:59 |
| sxpert | ah, they can't seem to be bothered to provide a menuentry file | 15:59 |
| daveshah | corecode: just adding blackboxes (i.e. verilog with only ports and parameters) for any new IP to https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v | 15:59 |
| tpb | Title: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at github.com) | 15:59 |
| sxpert | bouahahaha "I verify that I am not an employee of Cadence Design Systems, Mentor Graphics Corporation, or Magma Design Automation" | 16:04 |
| sxpert | hmm, the service pack .deb is installed, and the stupid thing doesn't see it | 16:12 |
| MoeIcenowy | I wonder whether the "adaptive" license process of Lattice can prevent any piracy | 16:13 |
| MoeIcenowy | ;-) | 16:13 |
| sxpert | wierd, I have both packages installed... where is the SP3 ? | 16:14 |
| sxpert | quality software detected ;-) | 16:15 |
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| corecode | daveshah: i'd love to get some feedback on the PR: https://github.com/cliffordwolf/icestorm/pull/202 | 17:56 |
| tpb | Title: iCE40 Ultra = iCE5LP = u4k port by corecode · Pull Request #202 · cliffordwolf/icestorm · GitHub (at github.com) | 17:56 |
| daveshah | corecode: sure | 17:56 |
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| corecode | thanks | 18:09 |
| corecode | seq_bits = icebox.get_lutff_seq_bits(ic.logic_tiles[(lut[0], lut[1])], lut[2]) | 18:09 |
| corecode | KeyError: (25, 19) | 18:09 |
| corecode | hmwhat | 18:09 |
| corecode | where did it get that from | 18:09 |
| corecode | yea, where does this ipcon_tile 25 19 come from | 18:13 |
| corecode | why can't it find that logic tile? because it is not a logic tile | 18:14 |
| corecode | hm. | 18:14 |
| MoeIcenowy | maybe someday I should try out a UL port? | 18:14 |
| corecode | yea if you have parts | 18:15 |
| MoeIcenowy | someone sells UL core board at Taobao for CNY ￥30 (~USD 5) | 18:15 |
| MoeIcenowy | although I think it has too few IOs | 18:15 |
| corecode | ok | 18:16 |
| corecode | well, i have a design that uses the u4k | 18:16 |
| corecode | 1k actually | 18:16 |
| corecode | how do i know which CBITs are set in a tile? | 18:22 |
| corecode | i see bits set in dsp3_tile 0 16 | 18:22 |
| corecode | but i don't know how B2[7] translates to CBIT_3 or CBIT_4 | 18:23 |
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| daveshah | corecode: so this would be looked up in the bit database built by icefuzz | 18:36 |
| daveshah | e.g. https://github.com/cliffordwolf/icestorm/blob/master/icebox/iceboxdb.py#L12110 | 18:37 |
| tpb | Title: icestorm/iceboxdb.py at master · cliffordwolf/icestorm · GitHub (at github.com) | 18:37 |
| daveshah | istr this bit doesn't exist in the database for dsp3_tile because there was no way to set it in icecube | 18:37 |
| daveshah | the ultimate solution is to try and add whatever is setting this bit to make_uip.py and rerunning the fuzzer | 18:38 |
| daveshah | then it will end up in the database as CBIT_x properly | 18:38 |
| corecode | why is this part of the dsp2 database? | 18:43 |
| corecode | does it just happen to sit there? | 18:44 |
| daveshah | no, I was using the dsp2 database as an example | 18:51 |
| daveshah | atm it exists only in the dsp2 database | 18:51 |
| daveshah | it should be in the dsp3 database too, but isn't because there was no way to set it on the ultraplus so icefuzz didn't add it | 18:52 |
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| MoeIcenowy | oh my god | 19:23 |
| MoeIcenowy | the ddr phy of Altera is not standard DFI | 19:24 |
| MoeIcenowy | but AFI (Altera PHY Interface) instead | 19:24 |
| MoeIcenowy | terrible. | 19:24 |
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