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| MoeIcenowy | sxpert: I think someone did initial RE on EP4CE6 | 02:18 |
|---|---|---|
| MoeIcenowy | BTW I have ordered a EP4CE115 board for CNY ￥495 (around USD $75) | 02:20 |
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| promach | is it possible that bmc passed at depth = 5 , but failed at depth = 10 ? Note that I am using "proof: depth 10" in sby file | 08:10 |
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| ZipCPU | promach: Absolutely! | 10:07 |
| ZipCPU | It's actually a common problem in one of my counter exercises. The counter gets set and starts counting down from 22, goes to idle, and then gets set and counts down again | 10:08 |
| ZipCPU | The only problem is ... we use a depth of 20 for the exercise, and there are often bugs at the point where the counter stops, waits, and restarts -- all at clock 22+, long after the 20 clocks necessary for the depth of 20 | 10:09 |
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| promach | ZipCPU: ok | 11:00 |
| promach | I know what went wrong in my code now | 11:00 |
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| corecode | what did? | 11:37 |
| corecode | daveshah: how should i proceed with this port? | 11:37 |
| daveshah | corecode: have you tested some small designs through icebox_vlog | 11:38 |
| corecode | not explicitly | 11:40 |
| corecode | i think some of the test scripts do that | 11:40 |
| daveshah | It would be worth trying a few designs manually and making sure the output is sane | 11:41 |
| corecode | i think at least i need to confirm the global networks & pins | 11:43 |
| daveshah | There are some Verilog designs for testing global networks in icefuzz/tests | 11:44 |
| corecode | yea, i will have to add some other footprint to cover all pads | 11:45 |
| daveshah | If it's anything like the UltraPlus, not every theoretical pad is covered even over all footprints... | 11:45 |
| corecode | what does that mean | 11:46 |
| daveshah | there are some IO locations that are not used in any package | 11:46 |
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| MoeIcenowy | maybe they will furtherly provide packages with more pins ;-) | 12:24 |
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| corecode | daveshah: hm, the ultralite datasheet says that global pin X is connected to global buffer X | 22:42 |
| corecode | is that different from global network X? | 22:42 |
| daveshah | No, it isn't | 22:42 |
| daveshah | global pin X drives global buffer X | 22:43 |
| daveshah | also, are you doing the ultra or the ultralite, btw? | 22:43 |
| daveshah | beware that the SB_GB which drives from fabric (as opposed to SB_GB_IO from the global pin) at the same location drives a different global network | 22:44 |
| corecode | ultralite, i think ice5lp | 22:44 |
| daveshah | ice5lp isn't the ultralite, it's the ultra | 22:44 |
| corecode | aha! | 22:44 |
| corecode | meh | 22:45 |
| corecode | why are they so bad with names | 22:45 |
| daveshah | the patch so far was the u4k, which is the ice5lp/ultra not the ultralite | 22:45 |
| daveshah | yeah, ikr | 22:45 |
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| corecode | daveshah: how would i force use of a specific global network? i'm trying to figure out the fabout locations | 23:24 |
| daveshah | corecode: you can constrain it in the icecube floorplan view, or in the pcf file | 23:24 |
| daveshah | I can't remember the syntax for the latter | 23:24 |
| corecode | aha | 23:24 |
| corecode | okay | 23:24 |
| corecode | i'll just skip the two padin that don't exist on this footprint | 23:25 |
| daveshah | icebox requires all 8 padins | 23:26 |
| corecode | ah | 23:26 |
| corecode | but there are not even 8 | 23:26 |
| daveshah | hmm | 23:26 |
| corecode | at least not documented | 23:26 |
| daveshah | the remaining ones should be at the same location as the fabouts | 23:27 |
| corecode | and what about the extra bits? | 23:27 |
| corecode | just keep them short? | 23:27 |
| daveshah | missing extra bits are fine | 23:27 |
| corecode | thank you | 23:27 |
| daveshah | it's only the padin_pio db that has to have 8 entries | 23:27 |
| daveshah | two of the extra bits will come from the oscillators | 23:28 |
| corecode | ah i guess it is called gbufin | 23:28 |
| daveshah | hopefully with oscillators and all packages all 8 extra bits will be covered in any case | 23:28 |
| corecode | i don't think so | 23:28 |
| daveshah | gbufin is the fabouts (x, y, global network) | 23:29 |
| corecode | ok | 23:30 |
| corecode | bit of a misnomer | 23:30 |
| daveshah | for some reason the documentation for it ended up in icebox_chipdb.py (the exporter) | 23:31 |
| daveshah | https://github.com/cliffordwolf/icestorm/blob/master/icebox/icebox_chipdb.py | 23:31 |
| tpb | Title: icestorm/icebox_chipdb.py at master · cliffordwolf/icestorm · GitHub (at github.com) | 23:31 |
| corecode | !!! | 23:32 |
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