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| emeb | corecode: what are you doing? | 00:03 |
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| corecode | emeb: actually i just want to try my forth cpu on an fpga | 00:59 |
| corecode | but icecube2 fails to place it | 01:00 |
| corecode | so now i'm - under protest - porting icestorm to the fpga i'm using | 01:00 |
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| emeb | corecode: interesting problem | 04:14 |
| emeb | which FPGA are you using? | 04:14 |
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| corecode | the ice5lp1k | 10:17 |
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| sxpert | daveshah: getting some messages from yosys when compiling about "assert" being used while read_verilog is not called with -sv on ecp5/cells_sim.v:41[1-4] | 10:19 |
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| mrec | I wonder is Clifford here? | 11:31 |
| daveshah | sxpert: hmm, perhaps an ifdef is needed | 11:37 |
| daveshah | mrec: no, not usually | 11:37 |
| mrec | some of his slides seem to be wrong ice40up5k doesn't have 128kbit bram, it's supposed to be 120kbit | 11:38 |
| mrec | 30*4k | 11:38 |
| daveshah | Indeed that is correct, I'll let him know | 11:38 |
| daveshah | The lp8k/hx8k does have 128kbit | 11:39 |
| mrec | http://www.clifford.at/papers/2018/nextpnr/slides.pdf | 11:39 |
| mrec | yes | 11:39 |
| mrec | well the specs are also wrong at the bottom of the pdf | 11:39 |
| * sxpert would like an ECP-5 100k with 8Mbit of bram ;) | 11:41 | |
| mrec | I'm happy with the ice40up for small items, the crappy linux spi implementation needs a lot cache | 11:42 |
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| daveshah | SPRAM would probably make sense | 11:44 |
| mrec | hmm is there anything better/faster/free available for simulating ice40 (mixed vhdl/verilog) designs than ActiveHDL? | 11:46 |
| daveshah | Mixed HDL, probably not | 11:48 |
| mrec | it takes quite a few seconds to simulate 10 milliseconds | 11:49 |
| mrec | more like a minute+ | 11:49 |
| daveshah | Verilator will be much faster, but is Verilog only | 11:49 |
| daveshah | it also might not support the vendor verilog models, because it doesn't implement the full event model, but it should work with the Yosys ones | 11:50 |
| corecode | i have no idea whether i am 10% or 90% done with the ul port | 11:52 |
| daveshah | If you want to create a PR or stick the repo somewhere I'm happy to take a look | 11:54 |
| corecode | thanks | 11:54 |
| daveshah | If you can get meaningful output from icebox_vlog for a few small designs from icecube (unpacked with iceunpack) then that's a good first step | 11:56 |
| * sxpert is happy, his decoder and alu can both be stalled at the same time by the bus controller | 11:56 | |
| sxpert | for example, when said bus controller will have to go fetch some dram data | 11:57 |
| corecode | daveshah: https://github.com/cliffordwolf/icestorm/compare/master...corecode:u4k?expand=1 | 12:05 |
| tpb | Title: Comparing cliffordwolf:master...corecode:u4k · cliffordwolf/icestorm · GitHub (at github.com) | 12:05 |
| corecode | some stupid whitespace changes in there as well - auto whitespace cleanup on save | 12:06 |
| daveshah | corecode: mostly looks good. Main comment right now is that the "_8k" RAM databases should be used, not the unprefixed (1k) ones | 12:18 |
| daveshah | The icebox changes all make sense | 12:20 |
| corecode | yea it's just that several of the icebox changes are not tested, just copied from the 5k | 12:45 |
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| promach_ | ZipCPU sxpert : https://gist.github.com/promach/5f2d9a9494704ed93cf65687c982198c had passed bmc, induction and cover() | 16:18 |
| tpb | Title: A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm · GitHub (at gist.github.com) | 16:18 |
| promach_ | and this multiplier code had also no problem with A_WIDTH != B_WIDTH so far | 16:20 |
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| promach_ | strange, when A_WIDTH = B_WIDTH = 4 , induction passed, but induction failed when A_WIDTH = B_WIDTH = 6 | 16:27 |
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| corecode | what is this sby file? | 17:04 |
| daveshah | sby is the config file for SymbiYosys, a wrapper around Yosys and various SAT/SMT solvers for formal verification | 17:05 |
| corecode | ah, thanks | 17:19 |
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