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| promach_ | ZipCPU: voodoo ? | 02:48 |
|---|---|---|
| promach_ | it seems like the cover(in_valid) failure got to do with initial assert() | 03:02 |
| promach_ | but I do not know why exactly this leads to cover() failure | 03:03 |
| promach_ | ZipCPU | 03:03 |
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| maikmerten | most surprising thing I found out in the last 24 hours: This does 1080p@60 VGA without glitching: https://pasteboard.co/I0vtcVD.jpg | 11:47 |
| tpb | Title: Pasteboard - Uploaded Image (at pasteboard.co) | 11:47 |
| maikmerten | I certainly would not have assumed that one can somehow drive a ~147 MHz pixel clock through such a setup, without any attempt of termination etc. | 11:48 |
| maikmerten | so the signals signals go FPGA board -> extension board with SRAM and Pmod -> Pmod connector -> Pmod to ISP cable adapter -> ISP cable -> ISP cable to Pmod adapter -> Pmod connector -> non-inverting bus driver with resistor DAC | 11:51 |
| sxpert | works as long as your total wire lengh < 1m or so | 12:05 |
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| maikmerten | "<sxpert> works as long as your total wire lengh < 1m or so" -- that sounds like a very thumby rule of thumb ;-) | 14:00 |
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| corecode | hi | 15:11 |
| corecode | i guess in the end i do have to port icestorm to my ice5lp, because icecube's placer fails with my design | 15:12 |
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| sxpert | maikmerten: it is ;) | 15:15 |
| sxpert | can I use "=" for a result that I need in a calculation immediately in an "always @(posedge clk)" block ? | 15:17 |
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| maikmerten | sxpert, yes, I'm pretty sure I used that once | 15:41 |
| maikmerten | sxpert, ended up removing that, though, because verilator does *not* allow that | 15:42 |
| maikmerten | (iverilog is okay with that style, though) | 15:42 |
| maikmerten | okay, yes, used that a while back | 15:43 |
| maikmerten | always @(negedge clk) begin | 15:43 |
| maikmerten | ... | 15:43 |
| maikmerten | if(!busy) state = nextstate; // assume new state NOW! | 15:43 |
| maikmerten | ... | 15:43 |
| maikmerten | case(state) | 15:43 |
| maikmerten | etc. etc. | 15:44 |
| maikmerten | I *think* that style isn't overly recommended, though | 15:45 |
| maikmerten | for reasons more experienced Verilog developers can surely elaborate on ;-) | 15:45 |
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| corecode | sounds you're mixing combinational logic and flops? | 16:23 |
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| sxpert | ok so it's frowned upon | 16:44 |
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| corecode | i'm by no means an expert, but separating (complex) combinational logic and clocked logic (flops) helps understand the design better | 17:22 |
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| lutsabound | sxpert: why not use an @* block instead? | 17:34 |
| somlo_ | daveshah: nextpnr PR #219 took me from 4:49:42 down to 0:17:26 (on a QEMU/KVM guest running on 2.4GHz Westmere hardware) | 17:35 |
| somlo_ | haven't actually tried programming the board (it's at the office), so I'll do that tomorrow | 17:36 |
| somlo_ | that's for the rocket-chip based blinky, to be precise | 17:37 |
| somlo_ | oh, and that was before you force-pushed a newer version of the PR | 17:39 |
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| sxpert | ok, I did what I wanted with another solution ;-) | 17:43 |
| sxpert | (do some of the stuff in a previous phase... | 17:43 |
| sxpert | as in, an actual different clock phase | 17:44 |
| sxpert | (add moar registers) | 17:44 |
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| sxpert | looks like the instruction set I'm going for is too complicated, needs more thought, single cycle instructions are not really doable | 17:48 |
| sxpert | the original is probably microprogrammed | 17:49 |
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| corecode | sxpert: what are you making? | 18:21 |
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| sxpert | corecode: implementing a saturn architecture | 21:11 |
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