Friday, 2019-01-25

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shapr	still didn't get zoom installed	00:06
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shapr	hi ZipCPU!	00:11
shapr	so I'm trying to get https://github.com/shapr/FPGA-Synthesizer working on the BeagleWire	00:12
tpb	Title: GitHub - shapr/FPGA-Synthesizer (at github.com)	00:12
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ZipCPU	Downloading it now	00:12
shapr	spiffy	00:12
ZipCPU	git pull didn't turn up any updates since the last ttime, some long time ago	00:12
shapr	from what you've taught me previously, I thought I could change the numbers used to do .. it's not clock division, wasn't there a different/better name?	00:13
ZipCPU	Hmm .... don't see any Verilator C++ files anywhere around here either ...	00:13
shapr	I found this on github, asked the author to add a license so I could use it	00:13
shapr	thing is, I have the same digilent pmod the author used	00:13
ZipCPU	synthesizer.v is the top module?	00:13
shapr	but a different clock speed	00:13
ZipCPU	Ooohh, okay	00:14
shapr	I think so?	00:14
ZipCPU	Do you have all the specification sheets?	00:14
shapr	yes, I can get the link	00:14
shapr	it uses i2s	00:14
shapr	this one: https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/	00:14
tpb	Title: Pmod I2S2: Stereo Audio Input and Output - Digilent (at store.digilentinc.com)	00:14
shapr	this claims to be the manual: https://reference.digilentinc.com/reference/pmod/pmodi2s2/reference-manual	00:14
tpb	Title: Pmod I2S2 Reference Manual [Reference.Digilentinc] (at reference.digilentinc.com)	00:14
ZipCPU	Yeah ... that's only part of what you need as I recall	00:15
shapr	in our previous discussion, daveshah pointed out that the line that says "500MHz" is wrong	00:15
shapr	this line: https://github.com/shapr/FPGA-Synthesizer/blob/master/synthesizer.v#L4	00:16
tpb	Title: FPGA-Synthesizer/synthesizer.v at master · shapr/FPGA-Synthesizer · GitHub (at github.com)	00:16
ZipCPU	I only see 50MHz on the reference page, so that would make sense	00:16
shapr	I think that becomes important when i2s is involved: https://github.com/shapr/FPGA-Synthesizer/blob/master/pmod_out.v#L39	00:16
ZipCPU	Keep going	00:16
tpb	Title: FPGA-Synthesizer/pmod_out.v at master · shapr/FPGA-Synthesizer · GitHub (at github.com)	00:16
ZipCPU	Hmm ... okay ...	00:17
shapr	I vaguely recall that this was developed on a Xilinx board, but I have forgotten the details of our previous discussion	00:17
ZipCPU	Do you have a trace of that code at all? (pmod_out that is)	00:18
shapr	I do remember we stopped when you pointed out that the phase of a signal must be preserved, I can't just change the divider numbers however I like	00:18
shapr	I have nothing	00:18
shapr	except this source, and a burning desire to get it working on the beaglewire	00:18
shapr	I also have nearly zero clue about FPGA design, just what I've heard here, and read in your tutorials.	00:18
ZipCPU	Ok, if you've read the tutorials, do you remember how cover() works?	00:19
shapr	I do not	00:19
* shapr quickly opens the tutorials		00:19
ZipCPU	I start discussing cover() in lesson 3	00:20
ZipCPU	Ever after that, we use it as part of our verification steps	00:20
shapr	I pretty much skipped the verification parts... figured I wasn't up to that yet	00:20
ZipCPU	Let's start that here: Add a line `ifdef FORMAL, followed by an `endif // FORMAL, and then we'll add some more between those	00:20
ZipCPU	Specifically, let's create a 10 bit counter: reg [9:0] counter; initial counter = 0;	00:21
shapr	in pmod_out.v?	00:21
ZipCPU	always @(posedge i_clk) counter <= counter + 1;	00:21
ZipCPU	Yes, in pmod_out.v	00:21
ZipCPU	Then you can say, always @(*) cover(counter == 10'd350); // for example	00:21
ZipCPU	(You do have SymbiYosys installed, right?)	00:22
shapr	should I add the always code later in the file like the rest of the code?	00:22
shapr	er, I don't think I have SymbiYosys installed	00:22
shapr	but I can install it.	00:22
ZipCPU	You'll need it installed to do this	00:22
ZipCPU	Installing it requires the installation of some other things as well ... might take a while	00:22
ZipCPU	I can do this here if you'd rather, and then just post the results ....	00:23
shapr	ok, seems to be installed	00:23
shapr	last night I built and install icestorm, yosys, arachne-pnr, and nextpnr	00:23
shapr	should have asked for a list of requirements	00:24
shapr	oh, more pieces need installing	00:24
ZipCPU	SymbiYosys also requires yices and boolector, with options for z3, avy, suprove, and some others	00:25
ZipCPU	We'll work with what you have	00:25
shapr	well, six core Xeon	00:25
shapr	so glad clifford's software all supports make -j N	00:26
ZipCPU	Ok, let's see if I can get a trace now ...	00:26
ZipCPU	It's running ...	00:26
shapr	what are you getting a trace for?	00:27
shapr	I think I'm missing lots of context	00:27
ZipCPU	I just want to see what this thing does	00:27
shapr	oh ok	00:27
ZipCPU	It helps to be able to visualize things	00:27
shapr	the way I understand synthesizers, you have several types of waveforms, square/sawtooth/?	00:27
shapr	and you stick them together to make noise	00:28
shapr	and the rest of this code talks to the pmod via i2s	00:28
ZipCPU	Ok, I have a screen shot to share ...	00:29
shapr	ooh yes?	00:29
ZipCPU	https://imgur.com/4c7ys6F	00:29
tpb	Title: Imgur: The magic of the Internet (at imgur.com)	00:29
shapr	my room is heating up while I build z3	00:30
ZipCPU	That shows you the code modifications to pmod_out.v, and the sby file I created	00:30
ZipCPU	I named the sby file: pmod_out.sby	00:30
ZipCPU	To run, just type: sby -f pmod_out.sby	00:30
* shapr takes notes		00:31
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ZipCPU	Then to view the trace, type: gtkwave pmod_out/engine_0/trace0.vcd	00:31
ZipCPU	Looks like our trace isn't quite long enough ;)	00:31
shapr	you can tell that because one of the lines only makes a single transition from zero to one?	00:32
shapr	is that right?	00:32
ZipCPU	Really long traces are a challenge to formal. While creating a trace is easy, getting a long one can take some work	00:32
ZipCPU	Yes, that's right	00:32
shapr	sclk to be specific	00:33
ZipCPU	Let's see if I can exhaust (i.e. formal) out to 2052 steps ... usually this is too far ...	00:33
ZipCPU	Well, not just the sclk, but also the lrclk	00:33
ZipCPU	The lrclk should toggle with every switch from the left speaker to the right speaker	00:33
ZipCPU	(and back again)	00:33
shapr	oh, I hadn't noticed lrclk	00:33
ZipCPU	I've made it to 1200 ... still going ...	00:34
ZipCPU	... it's starting to slow down ....	00:34
shapr	uh oh	00:35
ZipCPU	I asked it to go to 2052. Normally, the longest trace I do is about 300 steps or so	00:35
ZipCPU	Usually those traces really load the system--it's much easier to get a long trace via simulation than formal	00:35
ZipCPU	I'm up to about 1800 now ...	00:36
shapr	maybe there's a bug?	00:36
ZipCPU	... and just realized there is a bug and this isn't going to work ... I created a 12'bit counter, and I wanted an 11'bit counter ...	00:36
shapr	that is, perhaps the transition doesn't happen because of a bug in the verilog?	00:36
shapr	how could a too-large counter affect this?	00:37
ZipCPU	Nah, I'm covering a counter--not a transition	00:37
ZipCPU	Using the cover statement, I'm asking the formal tool to find a way, any way, to make the statement true	00:37
shapr	how do you know what size counter you need?	00:37
shapr	oh right, SMT solver	00:37
ZipCPU	cover(expr); /// finds anyway to make expr true	00:37
ZipCPU	To see your lrclk_count "tick", you'll need at least 1600 steps	00:38
ZipCPU	Let's let this run again, and chat about the tutorial	00:38
ZipCPU	You say you've read through the tutorial?	00:38
shapr	I skipped all the parts about formal anything :-/	00:39
ZipCPU	Lol!	00:39
ZipCPU	... and you expected your code to work? ;)	00:39
shapr	I expected code to blow up in creative ways that would teach me something	00:39
ZipCPU	See, that's what formal is for: to get the code to blow up in strange and creative ways--but where and while you can watch it	00:40
shapr	ok, fair point	00:40
ZipCPU	When the code blows up in strange ways on the hardware, you might wonder what's going on and have no way to figure it out	00:40
ZipCPU	Doesn't Haskell have a sort of "correct-by-design" methodology within it?	00:40
shapr	it does, but you get to choose your level of correctness	00:41
ZipCPU	Tell me, how so?	00:41
shapr	you can ignore all the safety if you want, or you can use the type system to check everything	00:41
ZipCPU	Do you tell it what to check, and what checks need to be valid?	00:41
ZipCPU	(Yes, there is a reason to my topic diversion here ...)	00:42
shapr	sort of, you could use a list in all sorts of ways, or you could define a datatype that acts like a list but constrains how you can use thta list	00:42
ZipCPU	How about a counter? Can you create a counter and then insist that it stay between 0 and say 62?	00:42
shapr	you can, yes	00:42
shapr	though it's not simple to constrain a value like that, it's doable	00:42
ZipCPU	I ask because formal methods are something kind of similar to that	00:43
ZipCPU	By constraining values to only those values something should have, and expressing relationships between things using formal, you can guarantee that when you place your design on actual hardware that it works	00:43
shapr	from what I know about SMT solvers (such as z3) you can ask it to find some combination of inputs that sets certain values to true or false	00:43
shapr	you're convincing me :-)	00:44
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ZipCPU	Yes	00:44
ZipCPU	https://imgur.com/6iTk9jN	00:44
tpb	Title: Imgur: The magic of the Internet (at imgur.com)	00:44
ZipCPU	There's our updated trace	00:44
ZipCPU	You can now see the lrclk toggle	00:44
shapr	it's long	00:44
ZipCPU	Well ... yeah	00:45
ZipCPU	That was part of the hassle	00:45
ZipCPU	I would've expected that the LRclk needed to toggle with the rise in MCLK	00:45
ZipCPU	I might need to go back to the spec to verify that though	00:45
* shapr looks at https://en.wikipedia.org/wiki/I%C2%B2S		00:45
ZipCPU	Have you looked at this at all: https://statics.cirrus.com/pubs/proDatasheet/CS5343-44_F5.pdf	00:46
shapr	nope	00:46
ZipCPU	Heheh ... okay, let's start at the top	00:46
shapr	the wikipedia page for I2S shows a timing diagram	00:46
ZipCPU	First things first with any project or hardware. Once you get/acquire/purchase hardware, the first thing you want to do is to gather some files together. Among these files are the schematic for the board, and the data sheets for all of the chips on the board	00:47
ZipCPU	Also grab any documentation the vendor provides	00:47
ZipCPU	Grab this at the beginning of any project, lest the vendor make updates to things and not (necessarily) tell you about them.	00:47
shapr	ah, like vendoring a library when building an application	00:47
ZipCPU	Not familiar with the term	00:48
shapr	get a version of a library saved locally so when you become familiar with its bugs, etc things don't change out from under you	00:48
ZipCPU	That said, most of my projects have a core directory structure with two entries: refs/ for all of these reference files, and trunk/ for all of my project files (left over from those old svn days)	00:48
ZipCPU	Yes!	00:48
shapr	ok	00:49
* shapr makes more notes		00:49
ZipCPU	Some projects also have a third directory, xilinx/, in which I force the vendor to place all their specific stuffs into	00:49
shapr	why so?	00:49
ZipCPU	This directory is not covered under git	00:49
shapr	is that for generated outputs?	00:49
ZipCPU	That makes it easy to blow it away and rebuild it, without worrying about damaging any source files	00:49
ZipCPU	Yes	00:49
shapr	ok	00:49
ZipCPU	It's for the project file, generated outputs, reports, etc	00:50
ZipCPU	Most of the fun parts of a project are within the trunk/ directory	00:50
shapr	right, makes sense	00:50
ZipCPU	Within that directory you get an rtl/ subdirectory for all the Verilog, a bench/cpp for all the C++ test bench stuffs, and a bench/formal for all my sby files and a Makefile to run them	00:50
shapr	ok	00:51
ZipCPU	If software is involved in the project (other than the bench tests), I'll often create a sw/ directory. sw/host will hold the things that run on my host (i.e. PC) computer	00:51
shapr	do you also have a top level Makefile so you can make clean to blow away generated files in xilinx/ ?	00:51
ZipCPU	(I had someone try and run PC programs on the ZipCPU, so I make a distinction there)	00:51
ZipCPU	No	00:51
ZipCPU	One of the items on my bucket list is to finally figure out how to "make" a Xilinx project	00:52
ZipCPU	I haven't figured it out yet, although it doesn't look all that hard to do	00:52
ZipCPU	The other problem with removing the xilinx/ directory is ... some of the items within there can take many minutes to build. You don't normally want to delete it therefore, although there will be times when Vivado isn't treating you nicely and ... you get the picture.	00:53
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ZipCPU	So for this project, you really need a bench/formal directory (to make sure the surprises happen where you can watch and understand them) and a bench/cpp directory (for long term simulation)	00:53
ZipCPU	The files themselves can be moved into an rtl/ subdirectory	00:53
ZipCPU	This doesn't need to be done now	00:54
shapr	ok	00:54
ZipCPU	(Perhaps when we are done0	00:54
ZipCPU	)	00:54
* ZipCPU pulls up the spec sheet pdf he downloaded		00:54
ZipCPU	Did you download the Cirrus Logic spec sheet?	00:54
shapr	no, I've been building my way towards SymbiYosys	00:55
* shapr downloads		00:55
shapr	ok, got it	00:55
ZipCPU	Check out page 10	00:55
shapr	I'm accustomed to working at the adafruit level	00:55
shapr	Lady Ada tends to make clear documentation meant for newbies	00:55
ZipCPU	Lol ... this is the level I've been successful working at	00:55
ZipCPU	This is also how I've managed to answer so many questions on Digilent's forums--by looking for the underlying spec sheets and reading them	00:56
shapr	what's a left-justified interface?	00:56
* ZipCPU hasn't answered nearly as many Digilent forum posts recently		00:56
ZipCPU	Most significant bit first	00:56
shapr	oh, huh	00:56
shapr	never would have guessed that	00:56
shapr	there are two different chip numbers	00:57
ZipCPU	That's one of the big things about I2S ... by placing the MSB's to the left (i.e. first), you can send only as many bits as you have and then just stuff things with zeros	00:57
shapr	does this mean there are two chips in the pmod?	00:57
ZipCPU	No	00:57
ZipCPU	It means the vendor built two chips but only put the time into writing one spec	00:58
ZipCPU	Why write two specs if you can stuff all the information into one?	00:58
shapr	so next step is to figure out which chip is in the pmod I own?	00:58
ZipCPU	Exactly! That should be marked on the schematic	00:58
shapr	aha, 5343	00:58
shapr	according to the digilent webpage at least	00:58
shapr	the chip difference appears to be something about the lrclk being to the left?	00:59
shapr	what should that tell me?	00:59
ZipCPU	Ok, I like your I2S chip ... there's no nasty set of 50k registers to set up in order to do anything useful	00:59
ZipCPU	What page are you reading that from?	01:00
* shapr opens a window to keep his laptop from overheating		01:00
shapr	same page 10	01:00
shapr	I'm trying to see the difference between the cs5343 and the cs5344	01:00
ZipCPU	Yeah, okay, I see it	01:00
shapr	that is, what's different between the top and bottom timing diagrams?	01:00
ZipCPU	The difference is that on one chip, the MSB takes place while LRCLK changes, and on the other chip it takes place after LRLK changes	01:01
ZipCPU	*LRCLK	01:01
ZipCPU	While the change is minor, it's something you'll need to knwo	01:01
ZipCPU	know	01:01
shapr	ok	01:01
shapr	and the chip I have is where LRCLK changes before MSB is sent	01:02
ZipCPU	So ... what can we learn from this ... usually there's some good timing information ...	01:02
ZipCPU	Yes	01:02
ZipCPU	Ideally you'd want to formally verify that's the case	01:02
shapr	is it important to notice the phase of these signals as well?	01:02
ZipCPU	... or rather, that such is the case of what pmod_out produces	01:02
ZipCPU	Let's look up t_sclkw and t_stp	01:02
shapr	if sclk were inverted, would I still be able to send audio?	01:03
shapr	previous page	01:03
ZipCPU	Not sure	01:03
ZipCPU	Usually my goal is to follow the diagram given on a page like this, rather than to divert from it	01:03
shapr	does duty cycle imply the max or min window of time something has to change?	01:03
shapr	ok	01:03
ZipCPU	If you make the waveforms match this one, you know the design will work	01:03
ZipCPU	Is your clock, i_clk, running at 50MHz or 100MHz?	01:04
shapr	BeagleWire stock is 100MHz according to the docs	01:05
ZipCPU	Perfect! Our trace has the right timeunits then	01:05
ZipCPU	(There's got to be a way to change the timeunits, but 10ns has always worked for me)	01:05
shapr	er, what?	01:06
ZipCPU	So now we can measure how long the mclk is, as an example	01:06
ZipCPU	(You can see from the picture the duty cycle is 50% ..)	01:06
ZipCPU	Looks like 500ns for MCLK	01:06
shapr	somewhere in the verilog we set the unit to 10ns?	01:07
shapr	or is this for the formal stuff?	01:07
ZipCPU	The 10ns was the step size in the trace the formal stuff created	01:07
ZipCPU	There's got to be a way to match it to your design ... I've just never done it	01:07
shapr	ok, that's where they need to match	01:07
ZipCPU	So, if your design was using 50MHz (20ns) ... the two wouldn't match at this point	01:08
shapr	how does 50MHz translate to 20ns?	01:08
shapr	oh, each clock is X ns?	01:08
ZipCPU	Each clock period is some number of nanoseconds. So take 1 / (CLOCK RATE) and you should get 10e-9 for a clock rate of 100MHz, or 20e-9 for a clock rate of 50MHz	01:09
shapr	ok, that makes sense	01:09
ZipCPU	I'd like to know how the MCLK corresponds to a particular sample rate ... but I'd need to read the data sheet more	01:09
ZipCPU	That should be an important part of your design -- matching the two	01:10
ZipCPU	Ideally, you should be able to play a tuning note from whatever musical instrument, and also play a note on your FPGA and the two pitches should match	01:10
shapr	ok	01:11
ZipCPU	Let's see ... you'd be running this in slave mode, right? (Can't see why not)	01:11
shapr	no clue	01:11
* ZipCPU was looking at the wrong half of the chart		01:11
ZipCPU	Ok, then let me tell you: Yes	01:12
ZipCPU	Since you are providing the clock to the chip, the chip will act as the slave and you the master	01:12
shapr	means the clock is coming from the beaglewire?	01:12
shapr	ok, got it	01:12
ZipCPU	Yep!	01:12
ZipCPU	So the chip offers two useful modes for this SCLK period: Single-speed 384x mode, and single-speed 256x mode	01:12
ZipCPU	Oohh ... the SCLK period needs to directly relate to the sample rate (see the equation?)	01:13
shapr	how do you know they're useful for this?	01:13
* shapr looks for the equation		01:13
ZipCPU	It's about 5-lines from the bottom of page 9	01:14
shapr	oh, I see it	01:14
ZipCPU	An SCLK period of 500ns corresponds to a 31.25kHz sample rate if you run the equation and solve for Fs	01:14
ZipCPU	The last three lines give us some nice formal properties we can work with	01:15
shapr	why is there a negative value there?	01:15
ZipCPU	You can see from the trace we have SCLK falling on the LRCK edge, so that's good	01:15
shapr	sclk falling to lrck edge	01:15
shapr	why is that good?	01:15
ZipCPU	It's just that you've got some slop there	01:15
shapr	oh, ok	01:16
ZipCPU	Given when LRCK changes, SCLK must change within 20ns of that--two clocks basically	01:16
ZipCPU	In the trace we just generated, SCLK is falling at the same time LRCLK is changing--so that's perfect	01:16
ZipCPU	We can quantify that as: always @(posedge i_clk) if ((f_past_valid)&&(!$fell(o_i2s_sclk))) assert($stable(o_i2s_lrclk));	01:17
shapr	wait, I don't see sclk changing when lrck changes in the trace	01:17
shapr	sclk changes at 0.5 ns, right?	01:18
shapr	er, microsecond, sorry	01:18
ZipCPU	Hmm ... yeah, you are right	01:18
ZipCPU	I got it confused with the MCLK	01:18
ZipCPU	So, that'd be broken then--good catch	01:18
shapr	I'm just trying to verify that I can at least see what you're saying :-)	01:19
ZipCPU	Good, good	01:19
ZipCPU	Looks like I mucked around with it. (I'd forgotten about that) Let me revert back to what's in the repo and see if it changes anything	01:20
shapr	hm, super_prove_build fails to build, I can figure that out later	01:20
ZipCPU	Yeah ... I've struggled to get that one to build	01:21
ZipCPU	I don't use it, so it hasn't bothered me much	01:21
ZipCPU	I really spend all my time with yices and boolector	01:21
shapr	since I don't know what pieces I'll need, I'm just building everything in clifford's list	01:21
ZipCPU	;)	01:21
* shapr warms the room with make -j12 in extavy		01:22
ZipCPU	Lol	01:23
ZipCPU	So, ... I reverted back to the repo's version and now I'm getting a bunch of bugs ...	01:23
shapr	so right now you're trying to confirm that the verilog code in the repo matches the requirements in the spec sheet?	01:23
shapr	not surprised...	01:23
ZipCPU	Well, where else would you start?	01:23
ZipCPU	This is how I get things to work ... read the spec sheet, look specifically for the pretty drawings, and check the timings	01:24
shapr	I don't know where I'd start, so I'm confirming that I do understand what and why	01:24
ZipCPU	Ok, found the bug ... you can't initialize sig_temp to sig because sig isn't constant. (That's on my line 25)	01:25
ZipCPU	shapr: Yep! Start with the schematic and the data sheets	01:25
ZipCPU	Match the pins on your FPGA to the pins on the data sheet via the schematic	01:25
ZipCPU	Use the schematic to find the data sheets of relevance, then look for the pretty pictures	01:25
ZipCPU	Usually, there's also some kind of instructions as well as the pictures--things like, set this register to this to accomplish that	01:26
shapr	earlier you said this doesn't need a bunch of that?	01:26
ZipCPU	For example, my ethernet chip has a register that I can use to make the port lights blink manually	01:26
shapr	"no nasty set of 50k registers to setup"	01:26
shapr	huh, interesting	01:26
ZipCPU	Exactly. This chip is unusual among the I2S chips I've looked at, since it doesn't have an I2C (not I2S) requirement allowing/requiring you to (re)configure it	01:27
shapr	morse code :-D	01:27
ZipCPU	Well ... this is why I haven't started my own I2S journey	01:27
ZipCPU	It's not because I don't have the code, and its not because I don't have a board with I2S on it	01:27
ZipCPU	It's because I can't decide how to go about configuring the I2S that I have	01:27
ZipCPU	or rather ... the sound chip (with the I2S ports) that I have	01:27
* ZipCPU is still running the 2k samples to see if he destroyed the SCLK ...		01:28
ZipCPU	Ok ... cover just passed, let's look at this new/updated trace ...	01:29
ZipCPU	Ok, sclk is toggling with a 1us period	01:30
shapr	what does cover(&counter); actually do?	01:30
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ZipCPU	https://imgur.com/D15CbxA	01:31
tpb	Title: Imgur: The magic of the Internet (at imgur.com)	01:31
ZipCPU	&counter is an expression that will only ever be true if the and of all the bits in the counter is 1'b1	01:31
ZipCPU	cover() is a formal operator that instructs the formal tools (when using mode cover) to exhaustively examine your design to see if there is some way to make the expression within true	01:32
ZipCPU	So ... I'm using it to quickly get a trace of 2048 timesteps	01:32
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ZipCPU	If you now zoom in on the LRCLK transition, you can see that it takes place at a time where SCLK falls as well	01:33
shapr	yes	01:34
* ZipCPU backs up to take a peak at the rest of the project		01:34
shapr	I'd be perfectly happy being able to send noise out of the pmod	01:34
ZipCPU	Lol!	01:34
ZipCPU	Be careful ... you might find yourself sending silence out of it, and not realizing what you've done	01:35
ZipCPU	Did you write the osc_sine.v function?	01:35
shapr	nope!	01:35
shapr	I wrote zero of this	01:35
shapr	like I said, found it on github, seemed like the thing I wanted, asked the author to add a license	01:35
ZipCPU	I'm not sure I know of any hardware that can do a divide	01:35
ZipCPU	Some hardware can do multiplies, but divides? Those are ... two steps past reality	01:36
shapr	ohh, that line 19 in osc_sine.v ?	01:36
ZipCPU	No, not that. All the initial stuff is done by the synthesizer, not the hardware	01:36
shapr	so that'll need to change for it to work on this ice40?	01:36
ZipCPU	I'm more worried about linse 39 and 41	01:36
shapr	I think this was written for a Xilinx Zynq board?	01:37
ZipCPU	Those are divides by constants, so they might work ... since you could turn them into multiplies	01:37
ZipCPU	Yeah, this might not work on an ice40	01:38
ZipCPU	(Other things would)	01:38
ZipCPU	For example, what equation defines cos_curr from start to finish?	01:38
* shapr thinks		01:38
ZipCPU	cos_curr = cos_last - (sin_last / denom);	01:38
shapr	oh, right	01:38
ZipCPU	Ooohh ... line 50? That'd be really hard to do ... accept an arbitrary input, and divide a value by it?	01:39
shapr	never crossed my mind that some verilog only works on some hardware	01:39
ZipCPU	(Remember: divides are hard. Multiplies only work with special purpose hardware often called "DSP"s)	01:39
shapr	oh, that's what DSPs do?	01:39
shapr	I figured they did FFTs	01:39
ZipCPU	Most iCE40's don't have DSP's, although I think the 5k's have them	01:40
ZipCPU	Yes, the DSP's can be used to do FFTs--since you can't get around the multiplies within the FFTs	01:40
shapr	"Lattice iCE40HX4K - TQFP 144 Package"	01:40
shapr	according to the beaglewire description	01:40
ZipCPU	In my own FFT implementation, I have a minimum requirement of log_2(FFT_SIZE) multiplies	01:40
ZipCPU	Treat that as an HX8K part ;D It's good for it	01:41
shapr	man, I thought software devs got picky about stuff	01:41
ZipCPU	(The chip is identical)	01:41
shapr	does that mean it has DSPs?	01:41
ZipCPU	Nope!	01:41
shapr	oh	01:41
ZipCPU	You don't have any DSPs at all	01:41
shapr	well then	01:41
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shapr	no div for me	01:41
ZipCPU	That doesn't mean you can't do this, it just means you'll need to switch algorithms	01:41
ZipCPU	For example, why not do all the division on the BBB?	01:41
shapr	er, ok?	01:42
ZipCPU	Exactly!	01:42
ZipCPU	The BBB should be able to set the frequency of what you are doing, why not?	01:42
shapr	er, I guess?	01:42
ZipCPU	Have you seen my NCO article?	01:42
shapr	don't think so	01:42
* shapr reads https://zipcpu.com/dsp/2017/12/09/nco.html		01:42
ZipCPU	Yes, that one	01:42
ZipCPU	It makes the math easy	01:43
shapr	heh, "embedded embedded applications"	01:43
ZipCPU	Sigh	01:43
* ZipCPU wanders off to go fix that		01:43
shapr	My mother was an English teacher, I had that kind of thing drilled into me.	01:43
shapr	I could put up PRs to fix your blog if you like :-)	01:44
* shapr spots more typos		01:44
ZipCPU	My problem is ... I read things things in all kinds of formats ...	01:44
ZipCPU	I first build it in markdown, then add links, then try to read it on the page but often end up switching to markdown, ... etc, etc, etc	01:44
shapr	makes sense	01:44
shapr	I often see what I think I wrote	01:45
shapr	so, how do I set the frequency from the BBB?	01:45
ZipCPU	Good question, let's go back to the schematic	01:45
shapr	output a single frequency from the verilog, and have an input signal to move the frequency?	01:45
ZipCPU	Sure!	01:45
shapr	that wouldn't require division?	01:46
ZipCPU	It sort of depends upon how much work you want to put into the communication	01:46
ZipCPU	No division	01:46
shapr	could I write verilog that acts like division? or would that be too slow?	01:46
shapr	I assume I'll have space	01:46
ZipCPU	You actually do have space. I've placed a divide unit onto an 8k before with space left over for the CPU that uses it :D	01:46
ZipCPU	What you don't have is time	01:46
shapr	oh	01:46
shapr	divide unit takes multiple cycles?	01:47
ZipCPU	The code you have asks for a division to be accomplished in one clock cycle	01:47
shapr	ah	01:47
shapr	man, this is weirder than a C programmer writing Haskell	01:47
ZipCPU	My divide unit takes (roughly) 32 clock cycles to divide a 32'bit number by another one	01:47
shapr	oh wow	01:47
ZipCPU	Lol	01:47
ZipCPU	And the multiply unit? That's crazier	01:47
ZipCPU	I finally got a REALLY good multiply unit to work on my ice40	01:47
shapr	whew	01:48
ZipCPU	It costs half as much as any other one I might try	01:48
ZipCPU	However, it also costs about N+2 cycles for an N-bit multiply	01:48
shapr	multiply can be done in a single cycle, but division only if you have a DSP	01:48
ZipCPU	No, other way around	01:48
shapr	division can be done in a single cycle?	01:48
ZipCPU	Multiply can be done in one cycle if you have a DSP, division always takes many cycles (or a REALLY slow clock)	01:48
shapr	ohh	01:48
shapr	my brain is getting full	01:49
ZipCPU	So, since the iCE40hx8k doesn't have DSP's, my multiply algorithm takes N+2 clocks for an NxN multiply	01:49
ZipCPU	This is good, right?	01:49
shapr	yes!	01:49
shapr	exactly what I wanted!	01:49
shapr	drinking from the firehose!	01:49
ZipCPU	Ok, I do have a recommendation for you:	01:49
shapr	1. read the formal parts of the zipcpu tutorials	01:49
shapr	2. install all the tools	01:49
ZipCPU	Go back through the tutorial, and do all the exercises. Get them to work on your hardware	01:50
shapr	3. read ALL the zipcpu tutorial blog posts	01:50
shapr	yeah!	01:50
ZipCPU	That'll give you several examples to work with that are (roughly) similar to this one	01:50
shapr	spiffy	01:50
ZipCPU	It'll also give you a base to work with, so that you can understand this problem when you get to it	01:50
ZipCPU	Do you have a serial port to work with?	01:50
shapr	I sort of wish the beaglewire had DSPs, but I'm sort of glad it doesn't, I have to learn the real stuff	01:50
shapr	er, sort of	01:51
ZipCPU	Sort of?	01:51
shapr	I have an FTDI cable	01:51
shapr	I have some arduinos that only take serial input, don't have their own FTDI chips	01:51
shapr	I may have a serial pmod	01:51
shapr	I bought a whole bunch	01:51
ZipCPU	Serial pmod is good ... I think it's calld a Pmod USBUART	01:51
ZipCPU	Double check the power on it though--you don't want to be fighting with the BBB's power	01:52
ZipCPU	(There's a jumper that needs to be set properly)	01:52
ZipCPU	You might also have a serial port directly into the BBB---check your schematic	01:52
ZipCPU	That'd probably be the easiest one to work with	01:52
ZipCPU	(Remember: Download the schematic first ... that'll tell you what's hooked up to what)	01:53
shapr	I don't have a serial pmod	01:53
ZipCPU	The RaspberryPi as I recall had a serial port on its extension pad ... but I might need to check that	01:53
shapr	they do sell a usb to uart	01:54
ZipCPU	(I'm checking to see if I have a BBB schematic ...)	01:54
shapr	the BBB is way more complicated than the rpi, imo	01:55
shapr	also far more oshw	01:55
ZipCPU	Yes, I think you are right on that account	01:55
shapr	(see my earlier comments in #openfpga about the closed-ness of the rpi)	01:55
ZipCPU	There it is ... yes, you have a couple of UART's on your expansion header	01:56
shapr	oh good	01:56
ZipCPU	That's on the last page of the BBB schematic I have (page 11)	01:56
ZipCPU	Looks like you might even have 4 separate UARTs ... neat. Not sure what you'd use 4 UART's for .... but you have them	01:56
shapr	then I could talk to one of my arduinos that only have serial?	01:56
ZipCPU	Yes	01:57
ZipCPU	It's also an easy way to talk to your FPGA and figure out what's going on within it, and to tell the FPGA what you want it to do	01:57
shapr	how do you do that?	01:57
ZipCPU	The tutorial focuses in many ways on the serial port, so having one will make your task easier	01:57
shapr	serial from your desktop to your FPGA?	01:57
ZipCPU	Absolutely!	01:57
ZipCPU	Not only that, but imagine running a C++ program on your desktop with calls to readio(ADDR) and writeio(ADDR, VALUE); which you can use to read and write values within your FPGA	01:58
shapr	since I have the beaglewire daughterboard (cape?) perhaps some of the ice40 pins connect to uart pins on the bbb?	01:58
shapr	that would be handy	01:58
ZipCPU	You know, one value might set the frequency of your tone, and another the amplitude?	01:58
shapr	reminds me of ws2812 code I've written	01:58
ZipCPU	;D	01:58
shapr	yeah, I did that for neopixels, where I'd send RGB values for each pixel	01:58
ZipCPU	See ... this is another reason why you want to start with the schematic--it lets you know what toys you have to play with	01:59
shapr	got slow with 144 though	01:59
ZipCPU	What did you write the code with?	01:59
ZipCPU	As in, what hardware did you use to control your ws2812?	01:59
shapr	I was using the arduino IDE, it's sort of C++	01:59
shapr	I sent it text commands over the usb<->serial, and it set the ws2812 values	01:59
ZipCPU	Ok, even better, now imagine connecting that to an FPGA. You could toggle those lines as fast as they could go, instead of as slow as the arduino would go	01:59
shapr	that would be cool	02:00
shapr	I have an unreasonable number of ws2812	02:00
ZipCPU	Indeed, using the FPGA, you could probably toggle the lines too fast, so you'd need to make sure you ran at the right speed	02:00
ZipCPU	Ooohh, even better, why not use your FPGA to toggle several of them at once? ;)	02:00
ZipCPU	Lots of possibilities there.	02:00
shapr	power problems	02:00
ZipCPU	Let's get back and focus, though ...	02:00
ZipCPU	Start with the serial port.	02:00
shapr	ok	02:01
ZipCPU	On the BBB, you'll use a program called "minicom" to communicate with the serial port	02:01
shapr	I think I have several hundred watts worth of ws2812b in various form factors	02:01
ZipCPU	Lol	02:01
shapr	yup, familiar with minicom	02:01
ZipCPU	Perfect!	02:01
shapr	used that for talking to the arduinos	02:01
ZipCPU	Do you have any buttons on your BeagleWire?	02:01
shapr	yes, three	02:01
ZipCPU	Ooohhhh!!! You've got to try the button pressing project	02:02
shapr	https://elinux.org/File:Bw_title.jpg	02:02
tpb	Title: File:Bw title.jpg - eLinux.org (at elinux.org)	02:02
ZipCPU	See if you can get the button counter to count backwards like I did :)	02:02
shapr	backwards?!	02:02
shapr	is this a project on your blog?	02:02
ZipCPU	It's one of the projects within the tutorial, leading to a discussion of timing and why it's important	02:02
shapr	spiffy	02:03
shapr	ok, any more assignments or suggestions for next time?	02:03
* ZipCPU tugs at his beard		02:03
ZipCPU	Well, each of the tutorial lessons has an assignment or two within it	02:03
shapr	ok, do those	02:04
* shapr makes more notes		02:04
ZipCPU	In all likelihood, you'll come back before you've finished with those	02:04
ZipCPU	Do you have any LED's on your board?	02:04
shapr	yes, four	02:04
ZipCPU	Pmod LED?	02:04
ZipCPU	Four is fine	02:04
shapr	had lots of fun getting this to work: https://github.com/pmezydlo/BeagleWire/blob/master/examples/blink_leds/top.v	02:04
tpb	Title: BeagleWire/top.v at master · pmezydlo/BeagleWire · GitHub (at github.com)	02:04
ZipCPU	My example I think is for 8, but the homework lesson is to adjust it down to the number available on your board	02:05
shapr	and this was even more fun: https://imgur.com/a/qdOp2fl	02:05
tpb	Title: First verilog code that does something - Album on Imgur (at imgur.com)	02:05
shapr	and then I figured out how to get both displays on the 2x seven segment to count up	02:05
ZipCPU	I've got a fun video I'm hoping to post soon--tonight perhaps even	02:05
shapr	cool	02:05
ZipCPU	I managed to get my FPGA to create a scrolling FFT raster	02:06
ZipCPU	... and I want to share that video	02:06
shapr	not sure what that is	02:06
ZipCPU	I took it from the middle of Beethoven's 9th, starting when the Base singer joins the orchestra	02:06
shapr	oh	02:06
ZipCPU	No? We discussed this some time before	02:07
ZipCPU	It shows frequency usage over time	02:07
shapr	heh, first google hit is https://github.com/ZipCPU/fftdemo	02:07
tpb	Title: GitHub - ZipCPU/fftdemo: A demonstration showing how several components can be compsed to build a simulated spectrogram (at github.com)	02:07
ZipCPU	The current sound is always on the right, as the display scrolls left	02:07
ZipCPU	Yeah, that's the project	02:07
shapr	oh, the waterfall display	02:07
ZipCPU	Since then, though, I've added HDMI + DDR3 SDRAM support	02:07
ZipCPU	Yep!	02:07
ZipCPU	https://zipcpu.com/dsp/freq-teaser.html	02:07
tpb	Title: Frequency Resolution (Teaser) (at zipcpu.com)	02:07
shapr	yeah, my kiwiSDR has that, looks really cool	02:08
shapr	pretty!	02:08
ZipCPU	It's even more fun to play with	02:08
shapr	ok, so I have a bunch of notes, and I have logs so I can go back and re-read what you've taught me	02:08
ZipCPU	Although .... evey time my security officer gets vocal with me, she seems to overload the system	02:08
ZipCPU	Yes	02:08
shapr	security officer? I thought you were self-employed?	02:09
shapr	oh, I get it!	02:09
shapr	SO	02:09
shapr	ha	02:09
ZipCPU	She's a subcontractor for Shepherd Security Services	02:09
shapr	oh, neat	02:09
ZipCPU	It's a German firm	02:09
ZipCPU	Get it?	02:09
* shapr snickers		02:09
shapr	yes	02:09
ZipCPU	Just making sure! ;)	02:10
shapr	so my first task is to get all the tools installed	02:10
ZipCPU	Yes	02:10
shapr	and report bugs or whatever for things that don't work	02:10
ZipCPU	Ok	02:10
ZipCPU	Your next task is an echo project on your serial port	02:10
shapr	then do all the tutorials and homework	02:10
shapr	ok, sounds good	02:10
ZipCPU	You should be able to type into your serial port and get exactly what you typed back out --- for very little work	02:10
ZipCPU	That's lesson 1 of the tutorial	02:10
shapr	I don't think I have any desktop/laptop with a serial port	02:11
ZipCPU	Lesson 2 works with an LED, causing it to blink once / second	02:11
shapr	I'll have to check	02:11
shapr	sounds easy enough	02:11
ZipCPU	Use the BBB's serial port	02:11
ZipCPU	Log into the BBB and then start minicom	02:11
shapr	ok	02:11
ZipCPU	Let's see ... lesson 3 has you building your first state machine, to rotate through your LEDs--back and forth	02:11
shapr	does that mean the serial implementation gets written in verilog	02:11
shapr	and runs on the ice40?	02:12
ZipCPU	Yes	02:12
ZipCPU	The easy implementation in lesson 1, and then a more difficult implementation in lesson 9	02:12
shapr	ok, I'm sure I'll have more questions	02:12
ZipCPU	The easy implementation just connects the transmit and receive wires together	02:12
ZipCPU	That's the "easy" part	02:12
shapr	that is easy	02:12
shapr	loopback serial	02:12
ZipCPU	The harder one in lesson 9 has you decoding the serial port and then re-encoding it to send the results back	02:13
shapr	ok, I have it all written down	02:13
ZipCPU	You sure?	02:13
shapr	probably?	02:13
ZipCPU	Heheh ... I'll be here if you get stuck	02:13
shapr	:-)	02:14
shapr	ok, time to build and install stuff...	02:14
ZipCPU	I look forward to hearing good things back from you ;D	02:14
ZipCPU	Let me go back to playing with my raster ...	02:15
ZipCPU	Look for a tweet with a video, if all goes well	02:15
shapr	yay!	02:17
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keesj	how long does it take to like verilog (comming from VHDL) ?	06:23
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ZipCPU	Ask daveshah. He's one of the few that have made the transition successfully	13:48
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keesj	I am looking at some examples in the icestom git repo I am looking at https://github.com/cliffordwolf/icestorm/blob/master/examples/icestick/checker.v#L29	19:09
tpb	Title: icestorm/checker.v at master · cliffordwolf/icestorm · GitHub (at github.com)	19:09
keesj	I see next_xorshift32_state reused different times in the always block and kinda find that .. strange (compared to my understanding). I expect the next_xorshift32_state on the right side to .. only change value past the always block e.g. while the first line (28) modifies the next_xorshift32_state I expect this modification to not be visible on the next line (29)	19:12
daveshah	keesj: the modification is visible because a blocking assignment (=) is used rather than a non-blocking assignment (<=)	19:12
keesj	am I correct and if so.. I am corret in thinking only the last line (29) actually result in something?	19:12
keesj	A.. ok	19:13
daveshah	think of it like := with a variable in VHDL	19:14
keesj	and would this change be visible externally ? e.g. the stant changes be visible	19:14
daveshah	eh, it's complicated	19:14
daveshah	not in hardware	19:14
keesj	ok.. I (might ) get it..	19:15
daveshah	in simulation you get all kinds of ugly race condition possibilities that I can't exactly remember	19:15
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mms	Evening fellas	21:41
daveshah	Heya mms	21:42
mms	Has anyone done or know any comparison done between yosys and vtr?	21:42
daveshah	I'm not aware of any detailed comparisons	21:44
daveshah	Last time I looked Yosys' Verilog support was much broader than ODIN II's	21:44
mms	I see	21:45
mms	I guess I have to check their Verilog support, thanks daveshah	21:47
daveshah	Is there anything in particular you are interested in?	21:48
mms	daveshah, No. I'm really new to logic synthesis and I was looking to get an general overview of these two.	21:51
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sorear	mms: http://opencircuitdesign.com/qflow/index.html talks briefly about odin versus yosys	22:59
tpb	Title: Qflow (at opencircuitdesign.com)	22:59
sorear	note that standard cell technology mapping and LUT mapping are related but not quite the same problem	23:00
mms	sorear, thanks	23:03
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