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| promach | For https://paste.ubuntu.com/p/sXPq7rwBn9/ , why am I having error : async_fifo.sv:125: ERROR: Invalid array access. ? I am using yosys-smtbmc by the way | 02:55 |
|---|---|---|
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 02:55 |
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| promach | I have solved this | 03:17 |
| ZipCPU | promach: Uses SymbiYosys instead--it's easier to work with and offers you more verification capability | 03:23 |
| promach | yeah I am using sby | 03:24 |
| promach | ZipCPU: I am now having problem resetting 2D array in systemverilog | 03:24 |
| ZipCPU | Fun | 03:25 |
| ZipCPU | Resetting an array .. is that even legal on any hardware? | 03:25 |
| promach | https://paste.ubuntu.com/p/yzsJZVk7Q6/ | 03:25 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 03:25 |
| promach | I seem to have solved the resetting problem | 03:25 |
| promach | another error cam eup | 03:25 |
| promach | came up | 03:25 |
| promach | write_reset_synchronizer | 03:26 |
| promach | this is a afifo | 03:26 |
| promach | ZipCPU: I want to see how Jeff Bush implementation https://paste.ubuntu.com/p/npSJC57NdC/ fares in formal verification | 03:27 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 03:27 |
| promach | his logic is simple but I am not sure it is working well enough | 03:27 |
| * ZipCPU is struggling with internet problems right now and can't click on any links | 03:28 | |
| promach | ZipCPU: ok, 404 ? | 03:28 |
| promach | I will figured this out slowly then, this code is not urgent at all | 03:28 |
| ZipCPU | No, my router isn't allowing my laptop to connect to the internet without going through my desktop | 03:29 |
| ZipCPU | It's ... complicated | 03:29 |
| promach | strange wifi router, haha | 03:29 |
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| ZipCPU | It's not that strange ... it worked just fine this morning | 03:30 |
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| promach | ZipCPU: successfully solved my sby setup issue | 04:03 |
| promach | now I am going to focus on writing assert() and assume() , and cover() for the code | 04:03 |
| ZipCPU | Looks like I've also succcesfully solved my router issue as well | 04:04 |
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| ZipCPU | promach: You realize that only ASIC hardware will support that FIFO clearing function, right? | 04:07 |
| promach | yup | 04:07 |
| ZipCPU | FPGA Block RAMs can't do that | 04:07 |
| promach | ok | 04:07 |
| promach | I mean with reset, you could | 04:07 |
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| sorear | asic memories can't do that either, you've just created a big array of flip-flops | 04:43 |
| promach | logic [WIDTH - 1:0] fifo_data[0:NUM_ENTRIES - 1]; | 04:45 |
| promach | sorear : what would be your recommendation ? | 04:45 |
| promach | https://gist.github.com/promach/1854bb054bb751fdfe02a3e655266e8e#file-async_fifo-sv-L126 | 04:47 |
| tpb | Title: An asynchronous FIFO implementation from the book "The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits" · GitHub (at gist.github.com) | 04:48 |
| sorear | dunno, ->sleep | 04:48 |
| promach | good, sleep is the best recommendation, haha | 04:49 |
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| promach | For https://paste.ubuntu.com/p/BSZgbRStBY/ , why "mode cover" does not generate a vcd waveform for me ? | 08:24 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 08:24 |
| promach | use this paste instead https://paste.ubuntu.com/p/ZfPGWWSX3V/ | 08:27 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 08:27 |
| promach | see line 399 | 08:27 |
| promach | line 130 and 161 as well | 08:28 |
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| Cerpin_ | since i know a lot of the people who work on the open ice40 tools are here: is there a way to infer something like an open-drain pin on a microcontroller with the ice40 i/o tiles? | 08:49 |
| Cerpin_ | Err, with an internal pull-up, additionally | 08:49 |
| Cerpin_ | I think that's the main thing I don't know how to ensure gets used, actually... | 08:49 |
| Cerpin_ | (if there is a better channel for this, I apologize and can move my question over there) | 08:50 |
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| daveshah | Cerpin_: you should be able to do `assign q = x ? 1'bz : 1'b0;` | 09:32 |
| daveshah | pullup can be enabled with `-pullup yes` in your pcf file | 09:32 |
| daveshah | After set_io | 09:33 |
| daveshah | This is a weak pullup, on up5k you can enable a strong pullup with `-pullup_resistor 3P3K|6P8K|10K` | 09:34 |
| daveshah | as desired | 09:34 |
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| promach | I have my previous problem using https://gist.github.com/promach/1854bb054bb751fdfe02a3e655266e8e#file-async_fifo-sby-L23 | 10:11 |
| tpb | Title: An asynchronous FIFO implementation from the book "The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits" · GitHub (at gist.github.com) | 10:11 |
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| tmeissner | Hi everyone | 13:01 |
| tmeissner | Does anyone has experience with the bind command to bind a SV(A) module to a VHDL entity? | 13:02 |
| tmeissner | The simple case works for me, but what should I do if I have a block defined inside the VHDL entity? | 13:02 |
| tmeissner | I cannot access the signals inside this block becuase it's another scope inside the architecture :/ | 13:03 |
| ZipCPU | Morning, tmeissner! | 13:19 |
| ZipCPU | Yes, I have experience with the bind command | 13:19 |
| ZipCPU | You have a couple of options there. You can apply another bind to the sub-entity | 13:19 |
| ZipCPU | You can also use the dot notation to set values in the top entity to match particular values in the subentity. These might only be used by the bind component. | 13:20 |
| ZipCPU | That then gives you access to values within the subentity | 13:20 |
| promach | bind command is supported now in yosys-smtbmc ?? | 13:25 |
| tmeissner | It's not a sub-entity. it's a block inside a VHDL block statement | 13:25 |
| tmeissner | I'm going to have a espresso first, will look after the options after ;) | 13:25 |
| tmeissner | But tahnks anyway :) | 13:26 |
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| ZipCPU | promach: Try SymbiYosys--it's much easier to use than yosys-smtbmc | 13:27 |
| ZipCPU | SymbiYosys can be used to drive yosys-smtbmc, but not all engines use yosys-smtbmc. SymbiYosys will select and drive the correct engine for you | 13:28 |
| promach | SymbiYosys supported bind command now ? | 13:29 |
| ZipCPU | The commercial version has for quite some time now | 13:32 |
| promach | not all people have the commercial one though :| | 13:33 |
| ZipCPU | The commercial version has full SV and VHDL support, to include concurrent assertions | 13:34 |
| promach | so the non-commercial, free version which is non-verific does not support bind , [*1:$] , |=> , |-> , etc.. ? | 13:35 |
| promach | ZipCPU | 13:35 |
| ZipCPU | :D | 13:35 |
| promach | :( | 13:36 |
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