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| adamgreig | I have an ice40 hx8k design using a pll with a clock into GBIN0 (on the same cell as the X16/Y33 PLL); arachne places fine but nextpnr errors saying the PACKAGEPIN for the SB_PLL40_PAD must be GBIN5 (X16/Y0, the cell with the other PLL) | 01:44 |
|---|---|---|
| adamgreig | I'm guessing it's picked the other PLL and then complained that the pad input is not in that cell, but I'm not really sure | 01:44 |
| adamgreig | any ideas? | 01:45 |
| cr1901_modern | adamgreig: You may wish to talk to tnt in ##openfpga. He's been tweaking PLL stuff lately | 01:46 |
| adamgreig | thanks, I'll try him | 01:47 |
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| tnt | I'm a bit confused. I have `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b)) and $display(" %d", `MAX(0, $clog2(1 << 17) - 18)); | 16:52 |
| tnt | and this displays -1 ... I would expect 0 (and that's what I get with iverilog) | 16:53 |
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| ZipCPU | tnt: That might depend upon the type of _a and _b. Are they both signed, or not? | 16:58 |
| ZipCPU | If I re-interpret -1 as an unsigned value, it will always be the maximum value | 16:59 |
| tnt | well, one argument is 0 exactly and the other is $clog2 which I'd expect to be signed. | 17:00 |
| ZipCPU | ... and to how many bits is the result applied? | 17:00 |
| tnt | it's used as the width of something. | 17:00 |
| tnt | localparam XXX = MAX(0, $clog2(1 << 17) - 18); and XXX will be -1. | 17:01 |
| tnt | sorry, localparam integer XXX = ... | 17:01 |
| ZipCPU | Do you have a 5-10 line example somewhere that I could test? | 17:02 |
| tnt | ZipCPU: https://pastebin.com/MCxpuXwm | 17:04 |
| tpb | Title: module test; `define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b)) localparam intege - Pastebin.com (at pastebin.com) | 17:04 |
| ZipCPU | So is your problem iverilog or yosys? | 17:05 |
| tnt | yosys | 17:06 |
| tnt | I mean, MAX(0,-1) should return 0 ... | 17:06 |
| ZipCPU | Not if there's a type conflict between signed and unsigned ... but let me test this out | 17:06 |
| tnt | AFAIU contants like '0' or '18' should be 'integer' in verilog by default. $clog2 is also supposed to return an integer according to the spec I have. So everything in that expression is of type 'integer' which is a signed type. | 17:08 |
| ZipCPU | I see what's going on | 17:08 |
| ZipCPU | I'm using yosys for my test | 17:08 |
| ZipCPU | yosys has an assertion failure reading this code ... | 17:09 |
| ZipCPU | Verilator has a problem with this code too | 17:10 |
| tnt | What's wrong with it ? Seemed perfectly valid to me ? | 17:10 |
| ZipCPU | It may be that I modified it slightly to create a wire of width [X-1:0] | 17:11 |
| ZipCPU | If 'X' is 0, the wire has zero width | 17:11 |
| ZipCPU | Let me adjust it for a width of [X:0] ... that should help this example along | 17:11 |
| sorear | I thought it created a little endian wire of width 2 | 17:12 |
| tnt | yeah the -1:0 thing is how I noticed th eproblem ... because yosys would throw a warning about reverse part order and truncate the signal and strip out all my logic ... and I narrowed it to that constant being miscomputed. | 17:12 |
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| ZipCPU | I wonder if removing the macro would change anything | 17:13 |
| ZipCPU | ... | 17:14 |
| tnt | not really | 17:15 |
| tnt | initial $display("%d", ($clog2(1 << 17) - 18) > 0 ? 1 : 0); | 17:15 |
| ZipCPU | If not, then that eliminates one possible part of the problem. (Testing now) | 17:15 |
| tnt | this displays 1 ... so -1 > 0 | 17:16 |
| ZipCPU | What's the type of $clog(X)? That'd be a good question ... | 17:16 |
| * ZipCPU looks up the SV spec | 17:16 | |
| tnt | The way I understand 17.11.1 of http://staff.ustc.edu.cn/~songch/download/IEEE.1364-2005.pdf it should be 'integer' | 17:18 |
| ZipCPU | Ok, so the argument is always treated as unsigned. That doesn't tell me much of the result | 17:18 |
| ZipCPU | Yes, integer is what I've got here too | 17:18 |
| * ZipCPU greps through yosys code to find the $clog2 implementation | 17:19 | |
| ZipCPU | Looks to be in frontends/ast/simplify.cc ... | 17:20 |
| tnt | and is_signed is set to false. | 17:22 |
| ZipCPU | Yosys creates an integer with it ... | 17:22 |
| ZipCPU | Let's stuff a printf in there and see what integer comes back from $clog2 ... | 17:22 |
| tnt | mkconst_int(uint32_t v, bool is_signed, int width) | 17:22 |
| tnt | if you take the result of clog2 and put it in an integer, then use it ... it works. | 17:24 |
| ZipCPU | Really? Ok ... (still digging) | 17:24 |
| ZipCPU | What result are you using for $clog2? | 17:27 |
| tnt | What do you mean ? | 17:28 |
| ZipCPU | You are using 17 for the result of $clog2(1<<17), right? | 17:31 |
| ZipCPU | (Seems obvious I know ...) | 17:31 |
| ZipCPU | Having now instrumented simplify.cc to look at what yosys is doing internally ... I'm now more confused than I was before. | 17:32 |
| ZipCPU | Ahh ... that's why ... it's subtracting one from the argument ... so it's working on (1<<17)-1 | 17:33 |
| ZipCPU | That still doesn't make any sense | 17:34 |
| ZipCPU | Counting 1's bits would only work for values of the form (1<<x)-1 | 17:34 |
| tnt | ZipCPU: https://pastebin.com/PJupBJsD | 17:36 |
| tpb | Title: [Diff] diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bb4c97 - Pastebin.com (at pastebin.com) | 17:36 |
| tnt | this makes it works as I'd expect. | 17:36 |
| * ZipCPU searches on the definition of mkconst_int | 17:36 | |
| ZipCPU | But ... $clog2 *should* be an unsigned value | 17:42 |
| ZipCPU | It's like ssize_t ... there's no way it can be negative | 17:42 |
| ZipCPU | Subtracting 18 from 17u should result in -1, but in an unsigned context ... -1 is the largest possible value | 17:43 |
| tnt | There is no way it can be negative, but it should still be a 'integer' signed type as far as verilog is concerned. | 17:44 |
| ZipCPU | Yeah, okay ... I see that in the spec | 17:44 |
| ZipCPU | Thanks for bringing that back to my attention | 17:44 |
| ZipCPU | Can I convince you to create a pull request with this information in it? | 17:45 |
| ZipCPU | ... and an issue documenting that pull request? | 17:45 |
| tnt | Sure | 17:45 |
| ZipCPU | I'll have a chance in a couple of days to make sure it gets the attention it needs. | 17:45 |
| tnt | If you can comment on https://github.com/YosysHQ/yosys/issues/700 and associated PR at the same time :P | 17:51 |
| tpb | Title: Feature request: Finer grained control on Clock Enable usage · Issue #700 · YosysHQ/yosys · GitHub (at github.com) | 17:51 |
| ZipCPU | Is that your PR as well? | 17:53 |
| tnt | yes | 17:53 |
| daveshah | I understand Clifford is about to travel to the US. So there might be a little delay on this stuff right now | 17:54 |
| ZipCPU | daveshah: what path forward do you recommend? Can you accept pull requests? This one is pretty simple | 17:55 |
| daveshah | No, I don't have permission for that | 17:55 |
| ZipCPU | Ok, we'll just hold on to these for Clifford then | 17:56 |
| tnt | #700 might be a bit 'unrefined' option, but at least so far I've had a good experience with it. I think pretty much all the designed I used this with ended up smaller and faster. | 18:09 |
| daveshah | tnt: without min_ce_use: 8 runs of picorv32 `min = 53.88 MHz, avg = 56.57125 MHz, max = 60.05 MHz` | 18:21 |
| daveshah | with min_ce_use=4: 8 runs of picorv32 `icetime: min = 57.28 MHz, avg = 61.33375 MHz, max = 64.6 MHz` | 18:21 |
| daveshah | with min_ce_use=8: 8 runs of picorv32 `icetime: min = 57.14 MHz, avg = 62.78874999999999 MHz, max = 67.06 MHz` | 18:21 |
| daveshah | LGTM! | 18:22 |
| daveshah | 11% improvement is very nice | 18:22 |
| zkms | nice! | 18:22 |
| tnt | daveshah: nice :) | 18:24 |
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| kc5tja | ZipCPU: yt by any chance? | 22:08 |
| ZipCPU | What's up? | 22:08 |
| * ZipCPU is working on another tutorial lesson | 22:09 | |
| ZipCPU | Stuck on anything? | 22:09 |
| kc5tja | Apologies for disappearing for months; but I'm running into an issue with Verilator where it cannot find verilated.h. | 22:09 |
| kc5tja | My goal is to write an integration test for the SIA core using Verilator. | 22:10 |
| ZipCPU | Do you have verilated.h in your distribution? | 22:10 |
| kc5tja | Yes. | 22:10 |
| kc5tja | Let me be more precise. | 22:10 |
| ZipCPU | Ok, so this is just a gcc issue. Go on. | 22:10 |
| kc5tja | It's in the Verilator package. | 22:10 |
| kc5tja | I'm not finding it in the obj_dir directory, though. | 22:10 |
| ZipCPU | Oh, dear. But yet you can run it, right? | 22:10 |
| kc5tja | I can run other Verilator tests OK. | 22:11 |
| ZipCPU | Yes, you've been doing very nicely with it from what I saw last | 22:11 |
| ZipCPU | Go on | 22:11 |
| ZipCPU | Are you using the -exe flag? (I don't normally do so, but it might affect this) | 22:12 |
| kc5tja | http://chiselapp.com/user/kc5tja/repository/kestrel-3/artifact/d8600c5a160ed1e3 | 22:12 |
| tpb | Title: Kestrel-3: Artifact Content (at chiselapp.com) | 22:12 |
| kc5tja | That's my Makefile. It's basically where you and I left off last time. | 22:12 |
| kc5tja | This appears to work for you, but for me, I just can't get it to locate verilated.h. Any ideas? | 22:13 |
| ZipCPU | Yes | 22:13 |
| ZipCPU | I've had this problem (I think) once or twice when using -exe. I don't normally use -exe, so I don't have it that often. | 22:13 |
| ZipCPU | Does it create an obj_dir directory? | 22:14 |
| kc5tja | It does. | 22:14 |
| kc5tja | Actually, let me double check. | 22:14 |
| kc5tja | Like I said, been 2 months since I last did this. ;-) | 22:14 |
| ZipCPU | Is there a reason why your "make -j ..." command doesn't include a number of processors? (Let me check if this is even legal ...) | 22:14 |
| kc5tja | LOL...OK, egg on my face. | 22:15 |
| ZipCPU | Ok, -j with no argument is legal | 22:15 |
| kc5tja | I typed "rm -rf obj_dir; make verilator_test" and it not only succeeded to compile, but now it ran. | 22:15 |
| ZipCPU | o/ | 22:15 |
| ZipCPU | Glad I could help you! | 22:15 |
| kc5tja | Rubber ducking for the win, I guess. | 22:15 |
| ZipCPU | Wow, that was one of the easier questions I've managed to help some one with. Got any harder ones? (Those are more fun) | 22:16 |
| ZipCPU | ;) | 22:16 |
| * ZipCPU needs rubber ducks from time to time too | 22:16 | |
| ZipCPU | I remember a bug I was struggling with where I was *convinced* yosys was _BROKEN_! | 22:16 |
| qu1j0t3 | heh | 22:16 |
| ZipCPU | I had an assertion that if (A) then (B) must be true on the next clock. I could cover(A), but never cover(B) | 22:17 |
| ZipCPU | The assertion passed, cover(B) did not | 22:17 |
| ZipCPU | It took some time, but I finally managed to corner clifford and get him to look at my code. | 22:17 |
| ZipCPU | He found the line that essentially said: assume(!B);, and suggested that the error message needed to be more comprehensible | 22:18 |
| ZipCPU | Same sort of thing. I was quite frustrated with myself for not handling my own work, but ... sometimes we all need another pair of eyes. | 22:18 |
| daveshah | I've had some fun bugs like that | 22:19 |
| kc5tja | Now I have to make sense of the VCD output. Heh. | 22:19 |
| ZipCPU | I just hate bringing others in to stare at my ... bad designs | 22:19 |
| daveshah | Spent two days debugging the first stage bootloader DDR3 init of an Allwinner A64 processor | 22:19 |
| daveshah | Turned out I'd put a 240kohm resistor instead of 240 ohm for the memory's Zq calibration resistor | 22:20 |
| ZipCPU | Ouch! | 22:21 |
| daveshah | It's not as bad as when my SDR project worked fine with some standalone software but failed to calibrate when part of gnuradio | 22:24 |
| ZipCPU | Go on | 22:24 |
| daveshah | Basically, both the AD9361 and something within gnuradio defined a function with the same name and a similar purpose, to do with the position of the first one bit in a word iirc | 22:24 |
| daveshah | But the way the defined it differed by one | 22:25 |
| ZipCPU | Doh! That one would've been a pain to find! I'd never look there | 22:25 |
| daveshah | The dynamic linker chose the gnuradio one which subtetlty broke the AD9361 init code | 22:25 |
| daveshah | I only found it by dumping the SPI data sent and received over USB to a file and comparing it in both cases | 22:25 |
| daveshah | Eventually I found the specific command that was failing | 22:26 |
| daveshah | And traced this back to where it was implemented | 22:26 |
| ZipCPU | I would've groaned pretty hard on finding something like that | 22:29 |
| ZipCPU | That would've also probably ended my work day | 22:34 |
| kc5tja | This is one of the reasons why I'm not a terribly big fan of dynamic linking as it's implemented on Windows or Posix environments. But, I'm an old man screaming at clouds. ;) | 22:35 |
| kc5tja | OOH, I totally forgot that your code pulses the clock and nothing happens right on an edge. | 22:48 |
| kc5tja | That will take me some getting used to. | 22:48 |
| ZipCPU | Trust me ... it'll save you from some other bugs ... ;) | 22:48 |
| ZipCPU | That said, I'd love to hear an alternative | 22:48 |
| kc5tja | I'm very used to looking at the VCDs that yosys generates where things happen on edges. | 22:49 |
| kc5tja | (It's also how I typically did my unit tests in the past, since it was less code) | 22:49 |
| ZipCPU | I'd love to have things happen on edges | 22:49 |
| ZipCPU | I wish I could | 22:49 |
| kc5tja | I'm not saying it's wrong; it's different from what I'm used to by many years. Going to take some mental adjustment on my part. | 22:49 |
| ZipCPU | It took me some adjustment as well ... after a lot of frustrating debugging with Verilator | 22:50 |
| kc5tja | Everything will work great until it doesn't. ;) | 22:52 |
| ZipCPU | Yes. So IMHO, the design process is all about mitigating the pain when things don't work | 22:53 |
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