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| adumont | @zipcpu Hi, I'm @adumont from twitter | 14:11 |
|---|---|---|
| ZipCPU | Good morning/afternoon! | 14:12 |
| ZipCPU | Can I ask how old your yosys build is? | 14:12 |
| ZipCPU | Is it a recent build from github? | 14:12 |
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| adumont | @zipcpu #facepalm! indeed I was not using the latest yosys build I was using 0.7+606. | 14:14 |
| ZipCPU | Well, let's keep working together ... Go ahead and build and tell me what takes place next | 14:15 |
| ZipCPU | Let's get you from here to success | 14:15 |
| ZipCPU | Don't forget---you may want to switch mode from cover to prove, depending on what you want to do | 14:15 |
| adumont | @zipcpu: using Yosys 0.8+36 (git sha1 719e2940) (I believe I built it last week), it doesn't complay anymore! :) | 14:15 |
| ZipCPU | Can I tweet that in response? Let me look like the hero? :D | 14:15 |
| adumont | @zipcpu: sure, you solved the issue :) | 14:16 |
| * ZipCPU smiles broadly! | 14:16 | |
| ZipCPU | Feel free to come back here if you have other questions! | 14:16 |
| ZipCPU | It's just too difficult to have a conversation over Twitter | 14:17 |
| adumont | @zipcpu: noted :). thanks, I'll follow the tutorial. I'm really eager to learn about Formal Verification. | 14:18 |
| ZipCPU | There are other kind souls on this channel that may also be willing to help you out as well, should I not be available. | 14:19 |
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| adamgreig | in nextpnr-ice40, using lvds inputs, is it expected that i have to specify the negative input pin number instead of the positive one? | 15:19 |
| daveshah | It should behave the same as arachne-pnr | 15:19 |
| adamgreig | should arachne-pnr behave the same as the lattice docs sort of vaguely suggest? :p | 15:19 |
| adamgreig | I will try with arachne-pnr and compare | 15:20 |
| adamgreig | the chipdb has z=0 for -ve and z=1 for +ve, and ice40's isValidBelForCell returns false if z!=0 | 15:20 |
| adamgreig | (if lvds is enabled) | 15:20 |
| adamgreig | aha | 15:21 |
| adamgreig | nextpnr error message: ERROR: Bel 'X0/Y20/io1' of type 'SB_IO' is not valid for cell 'SB_IO' of type 'SB_IO' | 15:21 |
| daveshah | I am pretty sure what we do matches the hardware | 15:21 |
| adamgreig | but, arachne-pnr error message: fatal error: pcf error: LVDS port `adc_ain' not a DPxxB input | 15:22 |
| daveshah | The vendor tools might abstract that more | 15:22 |
| adamgreig | that's fair, I was just expecting to specify the A pin from the app note on lvds, but the arachne-pnr error makes it very clear to use the B input | 15:22 |
| adamgreig | thanks for the pointer :) | 15:24 |
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| adumont | Hi guys, I'm wondering if anyone could help me fix this warning when I pass verilator: | 15:59 |
| adumont | %Warning-WIDTH: ram.v:23: Logical Operator IF expects 1 bit on the If, but If's VARREF 'ROMFILE' generates 104 bits. | 16:00 |
| adumont | code looks like this: | 16:00 |
| adumont | parameter ROMFILE = ""; | 16:00 |
| adumont | if( ROMFILE ) $readmemh(ROMFILE, mem); | 16:00 |
| adumont | I guess there's a better way to put it, but I have been unable to find how. (right now I put this /* verilator lint_off WIDTH */, but I feel it's not the right way) | 16:01 |
| ZipCPU | Hello, adumont! | 16:20 |
| ZipCPU | IIRC, I have an example of this that works | 16:20 |
| * ZipCPU rummages through his file system | 16:20 | |
| ZipCPU | I used a generate statement | 16:21 |
| ZipCPU | generate if (ROMFILE == 0) initial $readmemh(ROMFILE, mem); endgenerate | 16:21 |
| ZipCPU | You can see the example here: https://github.com/ZipCPU/icozip/blob/master/rtl/icozip/memdev.v | 16:22 |
| tpb | Title: icozip/memdev.v at master · ZipCPU/icozip · GitHub (at github.com) | 16:22 |
| ZipCPU | That said, it builds -- I'm not sure if I've actually executed the $readmemh in that example to know that it works | 16:22 |
| adumont | @zipcpu thanks, I'll try that | 16:24 |
| adumont | @zipcpu: actually, simply putting ROMFILE != 0 did the trick and now verilator doesn't give that warning. cool :) | 16:28 |
| adumont | @zipcpu: been scratching my head with your tutorial's lesson 3 :), on page 42 of the pdf, you run the sby -f ledwalker.sby and it fails (on your screenshot). In my case, with your example files, it doesn't , it passes | 16:31 |
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| ZipCPU | Let me check | 16:48 |
| adumont | @zipcpu: I get this: http://termbin.com/uu4r | 16:52 |
| ZipCPU | Are you set for cover or prove mode? | 16:53 |
| ZipCPU | (You were set for cover mode--without a cover() statement, your design will trivially pass cover()) | 16:55 |
| adumont | your ledwalker.sby says mode cover on the 2nd line | 16:55 |
| adumont | I haven't modified that | 16:55 |
| ZipCPU | Yes. Remember what that mode line does? | 16:55 |
| ZipCPU | So, here's what you need to remember about the source files: they are meant for you to learn from. They aren't fully functional. The idea was to have you work with them to make them so. | 16:56 |
| ZipCPU | ... and, hopefully by so doing, to encourage you to learn all the more. | 16:56 |
| ZipCPU | Sounds like you've just learned something from the discussion ;) | 16:56 |
| ZipCPU | If you go back to the lesson, there was a discussion regarding cover and what it did | 16:58 |
| adumont | @zipcpu: ah indeed! I'll rewind a bit in the lesson | 17:01 |
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