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| maikmerten | I've switched to nextpnr-ice40 recently, but found that some seeds, my design would not work as intended. | 13:54 |
|---|---|---|
| maikmerten | https://docs.google.com/spreadsheets/d/112N3hGuBwdhUELS_-PhzIbzZsqG7G0bgPgXH-1xu-R4/edit?usp=sharing | 13:54 |
| tpb | Title: nextpnr-ice40 seed (extension board, no cache) - Google Sheets (at docs.google.com) | 13:54 |
| maikmerten | I never *noticed* such things with arachne-pnr (which may, of course, be luck) | 13:55 |
| maikmerten | how would one tackle such issues where simulation is fine, most synthesis runs are fine, but for *some* seeds things just don't work out? | 13:56 |
| daveshah | the best approach is to do a post-pnr simulation using icebox_vlog to go back to a netlist | 13:57 |
| daveshah | however, this won't simulate timing issues | 13:57 |
| daveshah | do you have any inverted clocks in your design? | 13:57 |
| maikmerten | I have only one clock, but the control logic acts on the falling edge, while stuff like the ALU, bus unit etc. act on the rising edge | 13:58 |
| daveshah | I would say these can cause weird timing issues because at the moment (this will be fixed soon in nextpnr's own timing analysis) they aren't taken into account. But the fact your design's Fmax is double your operating clock more or less, then this wouldn't be the problem | 13:59 |
| maikmerten | ah, okay | 14:00 |
| daveshah | do you rely on initialised bram? | 14:01 |
| maikmerten | yes (boot ROM), which is why I keep the system in reset for 2048 cycles | 14:02 |
| daveshah | great | 14:03 |
| maikmerten | there's a strange bram errata IIRC | 14:03 |
| daveshah | yup | 14:03 |
| daveshah | but 2048 cycles is more than enough to mitigate it | 14:03 |
| maikmerten | yeah, but I also need to make sure the cache tags are invaldidated on reset ;-) | 14:04 |
| maikmerten | and my horrible solution to that is to write zero to the cache tags one entry after another on each clock when reset is asserted ;-) | 14:04 |
| maikmerten | so... just in case this happens due to my usage of inverted clocks and thus skewing timing results... arachne-pnr wouldn't care for that because all it does it to keep signal paths short, no matter what the clock? | 14:07 |
| daveshah | the timing weighting in nextpnr isn't that big tbh | 14:07 |
| daveshah | I don't think this is an inverted clock issue | 14:07 |
| daveshah | assuming your duty cycle is near enough 50%, your design passes timing even considering the inverted clocks | 14:08 |
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| daveshah | *clock duty cycle | 14:08 |
| maikmerten | \o/ net split, woooo! | 14:08 |
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| maikmerten | okay, thanks :-) | 14:09 |
| maikmerten | guess I'll do similar tests with arachne-pnr. Perhaps I just was lucky all the time and I'll find out that some seeds for arachne-pnr fail as well | 14:10 |
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| maikmerten | tested again with arachne-pnr: https://docs.google.com/spreadsheets/d/112N3hGuBwdhUELS_-PhzIbzZsqG7G0bgPgXH-1xu-R4/edit?usp=sharing | 15:26 |
| tpb | Title: nextpnr-ice40 seed (extension board, no cache) - Google Sheets (at docs.google.com) | 15:26 |
| maikmerten | the good news is that I don't need to switch back to arachne-pnr | 15:26 |
| maikmerten | the bad news is that not hitting any problems earlier with arachne-pnr was most likely just luck | 15:26 |
| maikmerten | there must be some critical timing stuff going on in my design | 15:27 |
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| daveshah | it could be metastability? | 15:28 |
| daveshah | if you have different clock domains or external IO | 15:28 |
| maikmerten | only one clock driving everything | 15:29 |
| maikmerten | heh, perhaps a silicon defect in my iCE40 ;-) | 15:29 |
| maikmerten | these tests were conducted with external SRAM attached to the FPGA board, this would of course add considerable room for timing issues | 15:31 |
| maikmerten | but I distinctly remember issues appearing with BRAM-only as well | 15:31 |
| daveshah | I dare say it, but it might be worth seeing what happens in the vendor tools | 15:40 |
| daveshah | They do perhaps have better timing, and rule out any possible icestorm bugs | 15:40 |
| maikmerten | yeah, I might have to resort to that. I hear icecube2 is full of excellence. | 15:48 |
| maikmerten | wow, Lattice presents me a registration page via HTTP. Manually changing to HTTPS works... at least. | 15:52 |
| cr1901_modern | "icecube2" and "full of excellence" in the same sentence. I must've jumped between timelines recently... | 15:54 |
| maikmerten | timelines all right https://www.youtube.com/watch?v=izrzkS5xxuc | 15:57 |
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| maikmerten | oh my, icecube2 is 32 bit. Great. | 16:13 |
| maikmerten | awwwww, maaaaan. It wants a license file. They happily send me a license file tied to my NIC. And then it complains that license file does not match my NIC. Excellent! | 16:32 |
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| bluesceada | maikmerten, if you are in linux it might be due to icecube2 relies on using "eth0", newer distros don't use that naming scheme anymore | 17:39 |
| bluesceada | easy solution is to load the dummy module | 17:40 |
| bluesceada | then do ip link add dev eth0 type dummy | 17:40 |
| bluesceada | and give it any mac address you want with ip link set dev eth0 address 00:11:22:33:44:55 | 17:40 |
| maikmerten | oh my. That's excellence right there. | 17:42 |
| bluesceada | if you heard it with tuntap devices before, I prefer a dummy interface over that. At least on notebooks where you might use network-manager for all sorts of connections, a tuntap device sometimes can confuse it | 17:42 |
| maikmerten | thanks for the hints | 17:43 |
| bluesceada | it is anyway ridiculous "security", even on a 'real' eth0 device you can 1. rename it in software 2. often change the mac in software anyway ... | 17:44 |
| maikmerten | I guess that's manager-type security | 17:46 |
| maikmerten | bluesceada, cool, thanks, that worked wonderfully | 17:51 |
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| maikmerten | okay, I guess I see now why iCECube2 is not universally referred to as being excellent. | 17:59 |
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| mithro | Has anyone played with RAM4K initialization options on the ice40 before? | 18:37 |
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