| *** tpb has joined #yosys | 00:00 | |
| *** emeb_mac has joined #yosys | 00:08 | |
| *** kuldeep has quit IRC | 00:21 | |
| *** kuldeep has joined #yosys | 00:50 | |
| *** leviathan has joined #yosys | 02:02 | |
| *** pie_ has quit IRC | 02:10 | |
| *** emeb has left #yosys | 03:18 | |
| *** _whitelogger has quit IRC | 05:06 | |
| *** _whitelogger has joined #yosys | 05:08 | |
| *** _whitelogger has quit IRC | 06:41 | |
| *** TD-Linux has quit IRC | 06:41 | |
| *** jhol has quit IRC | 06:41 | |
| *** jhol has joined #yosys | 06:41 | |
| *** TD-Linux has joined #yosys | 06:42 | |
| *** rohitksingh has joined #yosys | 06:55 | |
| *** emeb_mac has quit IRC | 07:08 | |
| *** _whitelogger has joined #yosys | 07:26 | |
| *** AlexDaniel has quit IRC | 07:33 | |
| *** rohitksingh has quit IRC | 08:07 | |
| *** rohitksingh has joined #yosys | 08:35 | |
| *** leviathan has quit IRC | 08:46 | |
| *** rohitksingh has quit IRC | 08:49 | |
| *** xerpi has joined #yosys | 09:00 | |
| *** promach_ has joined #yosys | 09:27 | |
| promach_ | Does yosys support calling variables from modules from different hierarchy ? I think this is a feature provided by systemverilog "bind". Please correct me if I am wrong | 09:28 |
|---|---|---|
| promach_ | https://media.readthedocs.org/pdf/symbiyosys/latest/symbiyosys.pdf#page=24 | 09:41 |
| daveshah | promach_: that page refers to Yosys' Verific SystemVerilog support | 09:44 |
| daveshah | I don't think this feature is supported in Yosys on its own | 09:45 |
| promach_ | daveshah: so, not supported in yosys-smtbmc ? | 09:51 |
| daveshah | promach_: not supported in Yosys' own verilog frontend | 09:52 |
| daveshah | smtbmc is part of the solver interface and irrelevant here | 09:52 |
| daveshah | Indeed Yosys with Verific uses the same smtbmc | 09:52 |
| *** maikmerten has joined #yosys | 10:07 | |
| *** rohitksingh has joined #yosys | 10:16 | |
| *** rohitksingh has quit IRC | 10:22 | |
| *** rohitksingh has joined #yosys | 10:34 | |
| *** xerpi has quit IRC | 10:43 | |
| *** leviathan has joined #yosys | 12:08 | |
| *** dys has quit IRC | 12:20 | |
| *** promach_ has quit IRC | 12:30 | |
| *** rohitksingh has quit IRC | 12:31 | |
| *** dys has joined #yosys | 12:35 | |
| *** rohitksingh has joined #yosys | 15:04 | |
| *** emeb_mac has joined #yosys | 15:08 | |
| *** kuldeep has quit IRC | 15:41 | |
| *** kuldeep has joined #yosys | 15:47 | |
| *** AlexDaniel has joined #yosys | 15:48 | |
| *** sandeepkr has joined #yosys | 15:49 | |
| *** leviathan has quit IRC | 16:38 | |
| *** seldridge has joined #yosys | 16:52 | |
| *** rohitksingh has quit IRC | 16:59 | |
| ZipCPU | Wow. Just made my third pull request to Yosys. Guess I never thought of myself as nearly that capable. | 17:58 |
| maikmerten | congratulations! | 17:58 |
| ZipCPU | It took a lot of searching through the spec. I feel like I just spent the last 6 hrs spec searching to get it right. | 17:59 |
| maikmerten | at least there's a spec that one can spend 6 hrs with ;-) | 18:00 |
| ZipCPU | Lol | 18:03 |
| ZipCPU | It was the Sys Verilog spec, dated 2012 | 18:03 |
| *** rohitksingh has joined #yosys | 18:10 | |
| *** maikmerten has quit IRC | 18:29 | |
| *** rohitksingh has quit IRC | 18:41 | |
| *** seldridge has quit IRC | 18:45 | |
| *** seldridge has joined #yosys | 18:45 | |
| *** rohitksingh has joined #yosys | 18:58 | |
| *** seldridge has quit IRC | 19:07 | |
| *** rohitksingh has quit IRC | 19:20 | |
| *** bluesceada has quit IRC | 21:12 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!