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| alexandarkostovi | Hi | 14:31 |
|---|---|---|
| alexandarkostovi | I am having some problems with yosys | 14:31 |
| daveshah | hi | 14:31 |
| alexandarkostovi | https://www.irccloud.com/pastebin/D5fRjEel/ | 14:33 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 14:33 |
| alexandarkostovi | but top.v is there | 14:33 |
| daveshah | `-top` takes the name of the top module, not the top Verilog file | 14:33 |
| daveshah | that should just be `top`, if that is what your top module is called | 14:34 |
| alexandarkostovi | okay, so when doing: | 14:34 |
| alexandarkostovi | synth_ice40 top -blif top.blif | 14:35 |
| alexandarkostovi | it gives an error | 14:35 |
| daveshah | no, it should be synth_ice40 -top top -blif top.blif | 14:35 |
| alexandarkostovi | https://www.irccloud.com/pastebin/WwoTmAAt/ | 14:36 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 14:36 |
| alexandarkostovi | again error | 14:36 |
| daveshah | that is because your top module isn't called top | 14:36 |
| daveshah | you also need to give your Verilog to source to yosys, either by adding it as a command line argument or also calling read_verilog top.v before synth | 14:37 |
| alexandarkostovi | https://usercontent.irccloud-cdn.com/file/OJNK6zE2/Screenshot%20from%202018-07-29%2016-32-01.png | 14:37 |
| daveshah | so what is the full Yosys command you are calling? | 14:37 |
| alexandarkostovi | synth_ice40 -top top -blif top.blif | 14:39 |
| daveshah | ok, before that you need to do read_verilog top.v uart.v {plus any other Verilog files} | 14:39 |
| alexandarkostovi | will try, brb | 14:39 |
| alexandarkostovi | https://www.irccloud.com/pastebin/jMH0kypX/ | 14:40 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 14:40 |
| daveshah | clearly top.v includes defines.v, but defines.v doesn't exist | 14:41 |
| alexandarkostovi | seen, deleted, now it shows error for unexpected = | 14:42 |
| daveshah | that sounds like another syntax error | 14:42 |
| alexandarkostovi | saw it where it is | 14:45 |
| alexandarkostovi | now works | 14:45 |
| alexandarkostovi | thanks for help! | 14:45 |
| daveshah | no problem | 14:46 |
| daveshah | enjoy yosys! | 14:46 |
| alexandarkostovi | i defenetly do | 14:46 |
| alexandarkostovi | its awesome | 14:46 |
| promach_ | daveshah: why would multiclock induction failed at one line of the code, but the trace does not show that it failed ? is it possible ? | 15:55 |
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| ZipCPU | promach: Is it possible? Only if there's a bug in yosys. So far, every time you've made a similar statement there's been a bug in your code. | 22:24 |
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