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| cr1901_modern | Is there a feature freeze or something of yosys right now? Usually PRs I make are merged in a few days. These few have taken 20 and 10 days respectively | 05:17 |
|---|---|---|
| cr1901_modern | And I _still_ have a path bug to fix | 05:17 |
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| ZipCPU | cr1901_modern: A path bug? | 11:39 |
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| mattvenn | qu1j0t3: I've done some latency/jitter testing on a few keyboards | 13:47 |
| mattvenn | using a logic analyser on the USB and a relay to press the key. so no key travel taken into account | 13:47 |
| mattvenn | you can see some results and my sigrok setup here : https://github.com/Dygmalab/latency-testing | 13:48 |
| tpb | Title: GitHub - Dygmalab/latency-testing (at github.com) | 13:48 |
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| maikmerten | yay, my HX8K breakout board arrived. I find it funny that the FPGA device is still labeled "SiliconBlue", despite Lattice having bought them in... 2011? | 15:53 |
| daveshah | I suspect they just made one big batch of devboards ages ago | 15:54 |
| maikmerten | (manufacturing date seems to be 30th week of 2012...) | 15:54 |
| maikmerten | yeah, guess they just went the "big batch" route | 15:55 |
| maikmerten | another board in my local hackerspace also has the SiliconBlue marking | 15:55 |
| shapr | now I have to check my devboard when I get home | 15:57 |
| maikmerten | mouser still has hundreds available for immediate dispatch... wonder if Lattice outsourced the storage costs ;-) | 15:58 |
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| TD-Linux | yeah mine is also siliconblue | 16:18 |
| maikmerten | I guess we have pattern then :-) | 16:32 |
| mithro | Apparently they where about to throw away a whole stack when the icestorm stuff hit | 16:40 |
| maikmerten | would be interesting to get some data on how icestorm affected the adoption of those iCE FPGAs - but I guess there's none to be had :-( | 16:48 |
| mithro | maikmerten: Definitely not anything publically | 17:16 |
| sorear | I’m sure it helped sell devboards, but are those ever a meaningful fraction of volume? | 17:16 |
| TD-Linux | their volumes are probably enormous, some iPhones have ice40s | 17:17 |
| sorear | What would be interesting to know is if that or any other major use was caused by icestorm | 17:18 |
| sorear | idk if the timing is possible in that case specifically | 17:18 |
| mithro | sorear: Never underestimate how frequently people end up "using what they know" -- Probably a large number of people now know that lattice *exists* compared to previously only ever considering Altera / Xilinx | 17:18 |
| TD-Linux | yeah, I wouldn't be surprised if icestorm created more Diamond users as well :) | 17:20 |
| sorear | mithro: very true | 17:21 |
| mithro | Although after using icestorm and *then* using the proprietary tools, you might just never use FPGAs again :-P | 17:22 |
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| sorear | (is icestorm the only toolchain that supports macOS?) | 17:23 |
| mithro | I think so? | 17:23 |
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| sorear | It’ll be interesting to see what changes when the ecp5 stuff is ready | 17:33 |
| maikmerten | ecp5... as in Cyclone V? | 17:35 |
| maikmerten | oh, no, that's Lattice, too | 17:35 |
| maikmerten | (I have a few Cyclone II boards called "ep2c5" and got side-tracked by that) | 17:36 |
| sorear | There are a couple active projects but ecp5 seems closest | 17:38 |
| maikmerten | ecp5 looks really decent | 17:40 |
| maikmerten | guess it comes from a completely different design family than iCE, which just got aquired | 17:41 |
| sorear | Yes | 17:43 |
| maikmerten | huh, on the HX8K eval board the 12 MHz oscillator is apparently not connected to a pin that can drive the PLL?! | 17:43 |
| maikmerten | fatal error: bad constraint on `clk_12mhz': no PLL at pin J3 | 17:43 |
| * maikmerten is puzzled | 17:43 | |
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| mjoldfield | maikmerten: These are my blinky notes for the HX8K demo board http://mjoldfield.com/atelier/2018/02/ice40-blinky-hx8k-breakout.html | 17:51 |
| tpb | Title: Martin’s Atelier: iCE40 Blinky on HX8K Breakout (at mjoldfield.com) | 17:51 |
| maikmerten | mjoldfield, thanks | 17:53 |
| mjoldfield | maikmerten: YMMV, I am a complete newbie with this stuff. | 17:54 |
| maikmerten | we have something common then :-) | 17:54 |
| maikmerten | that's always nice! | 17:54 |
| maikmerten | mjoldfield, thanks, that actually helped | 18:03 |
| maikmerten | had to instantiate SB_PLL40_CORE | 18:03 |
| maikmerten | (instead of _PAD) | 18:03 |
| mjoldfield | Oh good | 18:03 |
| daveshah | sorear: we have a blinky for the ecp5 now built using a fully FOSS Verilog to bitstream flow, and ECP5 synthesis just got merged into Yosys today | 18:18 |
| daveshah | the P&R still needs work and tidying up before its something that others could actually build/use but we're aiming for a release at the end of the month | 18:19 |
| daveshah | this will still be very basic, probably just IO, logic and distributed RAM | 18:19 |
| daveshah | EBR, DSP, fancy IO features, etc will come over the next few months | 18:19 |
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| sorear | Ooh, thanks for the update | 18:33 |
| sorear | Will the EOM release also have ice40 vtr? | 18:34 |
| daveshah | yes, mithro is working on that | 18:35 |
| mithro | Yes, at this very moment | 18:35 |
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| mithro | Maybe even some support for Artix-7 stuff in VtR if I can figure out this ice40 timing stuff which would allow me to get back to that | 18:36 |
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