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| daveshah | mithro: yeah, they are much better | 05:52 |
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| keesj | my presentation was .. alright. I hope I did not tell to many fairy tales. I can not look into more details into those LUT4 thingies and ice040 | 08:25 |
| keesj | (also I have a few tinyFPGA boards comming my way, next to the icestick and .. the beaglebone capes) | 08:26 |
| keesj | I need to chose to either port my can controller to verilog/ice40 e.g. https://keesj.github.io/can-hdl/ or do home automation (emulating 433.92 Mhz remote and controlling my beamer using IR) | 08:28 |
| tpb | Title: Can HDL documentation Can HDL documentation (at keesj.github.io) | 08:28 |
| keesj | but if I understand correctly the ghdlsynth-beta might allow me to compile vhdl code on ice040 https://github.com/tgingold/ghdlsynth-beta | 08:29 |
| tpb | Title: GitHub - tgingold/ghdlsynth-beta: VHDL synthesis (based on ghdl) (at github.com) | 08:29 |
| keesj | Is anybody interested in VHDL in here? | 08:30 |
| daveshah | keesj: ghdlsynth is very experimental | 08:31 |
| daveshah | No, I think most people here are Verilog people | 08:31 |
| keesj | Thanks. I will try to focus more on the second project. it is probably a little to simple to learn about verilog but will be cool for better understanding yosys | 08:40 |
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| Kokjo | Would it be possible to implement a fpga inside another fpga. I do understand the it would not be efficient, but how would i do it and can it be done? what it the simplest way to do this? | 09:15 |
| daveshah | Kokjo: sure | 09:16 |
| daveshah | I think there are even some projects like that | 09:16 |
| daveshah | can't remember any names, but I know I've seen them before | 09:18 |
| Kokjo | daveshah: can you point me in the right direction, googling "fpga in fpga" leads nowhere... | 09:18 |
| daveshah | Kokjo: this is for coarsegrained interconnect | 09:20 |
| daveshah | http://www.clifford.at/intersynth/ | 09:20 |
| tpb | Title: InterSynth - Example-Driven Interconnect Synthesis (at www.clifford.at) | 09:20 |
| keesj | it it possibly also possible to run a simluator on a soft core | 09:20 |
| Kokjo | daveshah: you are the one reverseing the ECP5 fpga, right? | 09:20 |
| daveshah | Kokjo: s/reversing/documenting | 09:20 |
| daveshah | be careful | 09:20 |
| daveshah | Edmund will tell us off otherwise | 09:21 |
| Kokjo | im not sure i understand the difference... | 09:21 |
| daveshah | one word has negative/illegal connotations, the other one doesn't | 09:21 |
| cr1901_modern | Someone must've gotten a stern warning for this in practice. E.g. the terms "reversing/HX4K" used to be casually discussed. | 09:24 |
| cr1901_modern | (on Twitter anyway) | 09:24 |
| Kokjo | daveshah: oh, i see. I did not know that, maybe i have been playing too much ctf, reverse engineering to has a very neutral connotations to me. reverse engineering to me is just the process of obtaining enough knowlegde about the internals of something to make it do funny things. | 09:24 |
| daveshah | I don't think we were told off by anyone in the FPGA companies. | 09:25 |
| daveshah | It's more a general approach of attempting to work more with them more I suppose | 09:26 |
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| cr1901_modern | What does "always @(negedge 1'hx) begin" mean in verilog (yosys generates it sometimes while I experiment)? | 11:27 |
| daveshah | cr1901_modern: do you have a nice example where it is generated? | 11:30 |
| daveshah | it seems like it would come from a flip-flop without a clock | 11:30 |
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| cr1901_modern | Run yosys on this file: https://hastebin.com/yemomedoko.nginx >> | 11:37 |
| cr1901_modern | with this script: https://hastebin.com/lonilutuqo.rb (up until/not including extra) | 11:37 |
| cr1901_modern | I.e. yosys -qp 'script bram-man.ys :extra' -l bram_man.yrp | 11:38 |
| cr1901_modern | The output file bram-man-noinf will have it | 11:38 |
| cr1901_modern | I'm trying to force yosys to use LUTs for RAM to experiment w/ something | 11:41 |
| daveshah | cr1901_modern: what Yosys version are you on? not seeing it locally | 11:44 |
| cr1901_modern | Actually I lied, that was the wrong script | 11:44 |
| cr1901_modern | https://hastebin.com/eqexagakaq.rb Try this one | 11:45 |
| daveshah | thanks, looking into it now | 11:47 |
| daveshah | cr1901_modern: looking at the RTLIL it seems that the memory still uses read and write port cells internally, which Yosys doesn't dump to Verilog very nicely | 11:53 |
| daveshah | I don't think write_verilog is really supported without a `memory` pass first | 11:54 |
| cr1901_modern | There is a "memory" pass (minus "memory_dff"). I just did it manually. | 11:55 |
| cr1901_modern | But whatever, this is par for the course any time I need to black box test yosys. I modify one thing, and yosys generates stuff I don't expect | 11:55 |
| cr1901_modern | meaning I'll have to spend time reading thousands of lines of C++ just to understand what's going on, decide it's not worth it, and it forever remains a mystery | 11:56 |
| daveshah | I think it is memory_dff that you need, that merges the write flipflop into the write port | 11:56 |
| cr1901_modern | But that's what I deliberately removed to see if yosys would fallback to LUT RAM! | 11:57 |
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| cr1901_modern | I didn't expect that removing the memory_dff pass would make it so yosys couldn't properly utilize LUTs | 11:57 |
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| cr1901_modern | https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v#L28-L30 I like how when I run memory_collect on this toy design, $mem cells are _not_ generated | 12:04 |
| tpb | Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com) | 12:04 |
| daveshah | cr1901_modern: memory_dff and memory_collect works for me | 12:09 |
| daveshah | afail memory_dff is pretty much required | 12:10 |
| daveshah | *afaik | 12:10 |
| cr1901_modern | memory_collect doesn't generate a $mem cell for me even when memory_dff is enabled | 12:21 |
| cr1901_modern | and even though the code path to generate a $mem cell is travered | 12:21 |
| cr1901_modern | bleh, I'm going back to bed | 12:22 |
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| tinyfpga | cr1901_modern: ICE40 cannot use LUTs as RAM, only ROM | 15:16 |
| daveshah | tinyfpga: hi! just got the 85k board from Edmund, thanks | 15:26 |
| daveshah | Good encouragement to fix the current performance issue in my Trellis to PnR database importer | 15:27 |
| tinyfpga | daveshah: ill upload the kicad layout today so you can find the JTAG, SPI ports and know how the pins are mapped | 16:27 |
| daveshah | tinyfpga: Awesome, that would be great | 16:28 |
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| mithro | daveshah: I was going to complain to you about that :-P | 18:32 |
| mithro | daveshah: (The speed of the Treills database importer :-) | 18:33 |
| daveshah | mithro: i will port it to c++ from that crappy snek thing | 18:33 |
| daveshah | that fixed the routing graph builder, should fix the database deduplicator too | 18:33 |
| mithro | daveshah: Actually, I think it was the compiling side of things that was taking a long time? I didn't have a lot of time to investigate before I had to run and catch a train | 18:34 |
| daveshah | mithro: that shouldn't be more than 20-30 secs max and could easily be fixed. It takes 6-8 minutes to build the data first | 18:35 |
| daveshah | which is also the snek bit | 18:35 |
| daveshah | mithro: fyi https://github.com/SymbiFlow/symbiflow-arch-defs/pull/186 and https://github.com/YosysHQ/yosys/pull/581 | 18:35 |
| tpb | Title: ecp5: Adding Verilog sim models by daveshah1 · Pull Request #186 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 18:35 |
| mithro | Dunno, it's not like I can complain - the ice40 rr_graph generator is *super slow* because of all the debugging prints and stuff | 18:36 |
| daveshah | mithro: to be fair, even 10 minutes is nothing compared to downloading and installing Vivado or Diamond particularly if you have the internet connection of a mere mortal | 18:37 |
| daveshah | not that we can't be better | 18:38 |
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| daveshah | I might even get to solving those problems this weekend, now I have more motivation to do so | 18:38 |
| mithro | daveshah: Even if you have Google's connectivity - downloading Vivado takes more then 10+ minutes | 18:38 |
| daveshah | mithro: from memory when I was downloading it on uni's ridicuously fat pipe over the summer holidays I was definitely being limited to 1-2MB/s by Xilinx's side anyway | 18:39 |
| mithro | IIRC digshadow managed to download and get blinky working on an ice40 device (having never used icestorm before) while waiting for Vivado to download... | 18:40 |
| digshadow | ha yeah | 18:40 |
| daveshah | I'm not surprised. On a slow day you could probably get an end to end flow working from scratch in that time period | 18:42 |
| * TD-Linux is slightly miffed that the ice40 doesn't have any 5v tolerant ios | 18:44 | |
| cr1901_modern | tinyfpga: Just in case; I don't mean distributed RAM in this case | 18:47 |
| mithro | TD-Linux: What uses 5V's these days? :-P | 18:48 |
| daveshah | my guess is it's something not from these days | 18:50 |
| mithro | daveshah: Really interesting to see your work to add the ECP5 to Yosys | 18:51 |
| daveshah | mithro: There is one annoyance that still needs work | 18:51 |
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| daveshah | The ECP5 has a FF style that is very unusual, and not following the usual silicon style. Basically synchronous set/reset has priority over clock enable - so clock enable isn't really a clock enable but just a data enable. Yosys can't extract these as it stands, so that will be a small custom pass | 18:52 |
| mithro | daveshah: Interesting, I was looking at that recently myself | 18:53 |
| daveshah | mithro: After discussion with Clifford we agreed just to use TRELLIS_FF for now and leave the Lattice primitives for another time | 18:53 |
| mithro | daveshah: That actually sounds exactly how I would suggest you do it | 18:53 |
| daveshah | Lattice have a lot of FF primitives that are quite annoying to deal with, like FFs with a mux in front because one of their ancient architectures looked like that | 18:54 |
| daveshah | For RAM I may do the same, or support both. The Lattice primitives take a C-style hex number in a string rather than a Verilog numeric parameter for initialisation | 18:54 |
| daveshah | You'll see the conversion function I had to write in the DPR16X4C sim model (I wanted a Lattice-compatible DPRAM as an option, because some people manually instantiate RAM) | 18:55 |
| daveshah | somehow doing ASCII string processing in Verilog feels off | 18:56 |
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| TD-Linux | mithro, nothing, I'm trying to interface to 1992 hardware :^) | 19:03 |
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| mithro | daveshah: WTF :-P | 20:15 |
| daveshah | mithro: that's Lattice for you | 20:16 |
| daveshah | Layers upon layers of legacy that no one understands any more | 20:16 |
| daveshah | Oh wait that's almost any company | 20:17 |
| qu1j0t3 | ^ | 20:27 |
| daveshah | I'm not sure how much the core of Diamond has really changed since AT&T bought their NeoCAD license in '95 tbh | 20:31 |
| daveshah | That then was sold with the ORCA FPGAs to Lucent, then Agere who were finally sold to Lattice | 20:32 |
| daveshah | Many of the primitives seem to originate from the ORCA days | 20:33 |
| daveshah | Why am I now spending Friday night reading PDF manuals of FPGA flows from before I was born? What is wrong with me :P | 20:38 |
| mithro | daveshah: sounds about right | 20:46 |
| daveshah | mithro: it's where the weird FF primitives came from. Letters were expensive back them | 20:54 |
| daveshah | *then | 20:55 |
| daveshah | :P | 20:55 |
| mithro | daveshah: You say that - but one of the reason why unix commands are like 2 letters (like ls, cp, mv) is because typing on early terminals actually had very slow mechanical interlocks to prevent you pressing keys at the same time and causing shorts | 20:57 |
| daveshah | mithro: hehe | 20:57 |
| daveshah | I suspect the real reason is they were avoiding parameters for some reason, so they needed loads of different primitives | 20:58 |
| daveshah | And then they built on that with every new architecure over the last 25 years | 20:58 |
| daveshah | Tbh, I'm both impressed as to how advanced things were back then and depressed as to how little has changed, compared to the silicon itseld | 20:59 |
| daveshah | Wow | 21:02 |
| daveshah | https://www.electronicproducts.com/Software/FPGA_synthesis_goes_online.aspx | 21:02 |
| tpb | Title: FPGA synthesis goes online - Electronic Products (at www.electronicproducts.com) | 21:02 |
| daveshah | Cloud synthesis in 2000 | 21:02 |
| daveshah | Costing 15-60$ per run | 21:02 |
| sorear | now the question is what is that per hour at the speed of the tools in 2000 :p | 21:06 |
| daveshah | The biggest ORCA 3 part was about 6000 LUTs, which Yosys/arachne can do in maybe a minute or two max | 21:08 |
| daveshah | arachne's algorithms probably aren't much better than 2000 era, but might trade speed for QoR | 21:08 |
| daveshah | I can't imagine it would be more than an hour | 21:09 |
| mithro | daveshah: You might underestimate how much faster computers have gotten since the 2000s :-P | 21:11 |
| daveshah | mithro: I'm going to assume it would be running on reasonably high end machines back then | 21:13 |
| daveshah | It's hard to have a reference point because none of my uses of computers back then where really performance related | 21:14 |
| daveshah | My Pentium III laptop certainly felt fast enough back then | 21:15 |
| mithro | daveshah: 2000 was like ~Pentium 2 generation | 21:15 |
| mithro | 400Mhz P2 -- 64mb sdram running at 100 mhz | 21:15 |
| mithro | My 8088 felt pretty fast for a long time too -- definitely compared to my human abilities ;-) | 21:15 |
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| sorear | [yall have seen dan luu's input latency post?] | 21:20 |
| qu1j0t3 | yes.... we have..... | 21:22 |
| cr1901_modern | Err, mithro, how old are you again :P? | 21:22 |
| mithro | Good question - Born 1983 | 21:22 |
| cr1901_modern | I mean, I have an 8088 (a few) but I certainly didn't buy it when it was new. | 21:22 |
| cr1901_modern | Ahh | 21:23 |
| cr1901_modern | I thought you were closer to my age (1990) | 21:23 |
| cr1901_modern | Also, tbf, I didn't learn how to program/_really_ play w/ computers until I was 18-20 | 21:24 |
| mithro | 8088 was my first computer and it was second hand from what at the time was our monopoly telco | 21:24 |
| sorear | qu1j0t3: i'd be surprised if you hadn't, but still remiss not to ask | 21:24 |
| qu1j0t3 | :) | 21:24 |
| qu1j0t3 | we're still a bit confused by what he was measuring and unsure if anyone has reproduced the results. | 21:25 |
| qu1j0t3 | anyone who's used transcontinental ssh knows that 200ms latencies are all but unusable | 21:25 |
| sorear | do you mean intercontinental | 21:26 |
| qu1j0t3 | yes, inter- | 21:26 |
| qu1j0t3 | sorry | 21:26 |
| * mithro laughs at your 200ms -- Australia FTW! | 21:26 | |
| qu1j0t3 | who has time to duplicate his test rig? i suspect he has more free time than i do, so my rebuttal will probably never be written :D | 21:26 |
| awygle | maybe it's actually 400 ms latencies that are all but unusable | 21:28 |
| awygle | and half comes from network and half from *other* | 21:28 |
| qu1j0t3 | no, 200ms is awful | 21:29 |
| mithro | actually - latency isn't a huge problem - jitter is much worse | 21:29 |
| qu1j0t3 | latency is a problem. | 21:29 |
| qu1j0t3 | for me, anyway. | 21:29 |
| TD-Linux | dan luu's post takes key travel into account | 21:29 |
| qu1j0t3 | i know. | 21:29 |
| qu1j0t3 | which seems pretty bizarre | 21:29 |
| mithro | Humans will adapt to a fixed length latency pretty easily | 21:30 |
| qu1j0t3 | aren't we all typing on silly chiclet things nowadays? I mean, i'm not right now, i prefer proper keyboards | 21:30 |
| qu1j0t3 | mithro: I don't want to adapt to 200ms. Really. And I don't think you would either. | 21:30 |
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| qu1j0t3 | and i also don't believe we have, so luu's stuff smells funny. | 21:30 |
| TD-Linux | no, I'm typing on a real keyboard. I imagine many are, the "mechanical" keyboards have even become popular with gamers | 21:30 |
| awygle | i'm typing on a rubber dome keyboard :( | 21:31 |
| mithro | qu1j0t3: Until they improve the speed of light, Australia -> US or Europe latency is always going to suck :-( | 21:31 |
| awygle | i actually _like_ chiclets but i don't even have one | 21:31 |
| qu1j0t3 | i mean eventually arguments over Luu's piece may drive me to do my own measurements. | 21:31 |
| qu1j0t3 | mithro: I'm aware from first hand experience :D | 21:31 |
| awygle | at least at work | 21:31 |
| mithro | qu1j0t3: Your a fellow Australian expat? | 21:32 |
| qu1j0t3 | awygle: I have a 2012 MBP here with chiclets, i get used to it. I guess the Retina screen takes my mind off the keyboard. | 21:32 |
| qu1j0t3 | mithro: Yes, actually :) | 21:32 |
| mithro | qu1j0t3: Ha, didn't know that | 21:32 |
| awygle | qu1j0t3: i have, like, _really_ bad RSI issues so the low travel and light touch of chiclets help me enormously | 21:32 |
| TD-Linux | also a lot of the views of old computer latency seem to have rose tinted glasses. For the early 90's machines I have, I get to watch it recompute palette all the time | 21:32 |
| qu1j0t3 | mithro: (I assume you checked my hostmask, which is no longer indicative of my actual location) | 21:32 |
| qu1j0t3 | awygle: *nod* | 21:32 |
| awygle | (this is also why i tweeted that thing about hating using shift) | 21:32 |
| TD-Linux | and the apple II can't accept keyboard input while accessing the disk, like scrolling through a document | 21:32 |
| awygle | i certainly don't miss the computer going all "you just won solitaire" anytime i tried to do anything taxing | 21:33 |
| qu1j0t3 | TD-Linux: haha, i am pretty sure the BBC Micro doesn't have that problem | 21:33 |
| qu1j0t3 | TD-Linux: i don't recall any latency issues with machines i used in the 80s and 90s | 21:34 |
| qu1j0t3 | TD-Linux: or indeed the ones i use today *shrug* | 21:34 |
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| TD-Linux | qu1j0t3, yeah, well it has a real disk controller. the apple II has woz magic | 21:35 |
| qu1j0t3 | heheh | 21:35 |
| TD-Linux | also the apple II has no interrupts at all. | 21:35 |
| qu1j0t3 | the II was a bit dated by the time the Beeb came out. | 21:35 |
| sorear | they don't need to improve the speed of light, just run gas/vacuum waveguides in a trench through the mantle | 21:35 |
| qu1j0t3 | tell Musk, it might keep him out of trouble | 21:36 |
| awygle | na musk is a 10xer and that's only 3x | 21:38 |
| qu1j0t3 | lol | 21:39 |
| qu1j0t3 | i think at 5x they should get a truman show dome | 21:39 |
| qu1j0t3 | for the safety of the rest of us | 21:39 |
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