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| azzizi_ | 21:17 <azzizi> I had a question .........can I create a script using matlab or any other language and create a modified RTLIL and can Yosys work with that ? I mean can I input the modified RTLIL ? 21:20 <daveshah> azzizi: yes, of course, but I personally wouldn't want to try and parse and generate RTLIL in Matlab 21:20 <daveshah> Probably be faster to learn C++ 21:23 <daveshah> The relevant command is read_ilang though 21:24 <da | 15:45 |
|---|---|---|
| azzizi_ | 21:24 <daveshah> The Json format is also worth looking into as a way of processing designs in another language | 15:46 |
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| azzizi_ | <daveshah> thanks ...I am thinking about python ...but any idea how do input the newly created RTLIL to Yosys ..so it can work with the new RTLIL and get the backends work on it? | 15:47 |
| daveshah | azzizi: you can use read_ilang | 15:48 |
| daveshah | but ilang is not a stable or supported external format, its primarily for Yosys debugging | 15:48 |
| daveshah | I would really recommend looking at JSON instead | 15:48 |
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| azzizi_ | <daveshah> For my work, I think I could work on RTLIL ...it's fine that it's not supported..could you elaborate on "not stable" ? | 15:51 |
| daveshah | azzizi_: there is a risk it could change in new Yosys versions | 15:51 |
| azzizi_ | SO the rtlil needs to be transferred to JSON first and then worked on it ? | 15:53 |
| azzizi_ | dang ..never thought of this | 15:53 |
| daveshah | you should use "read_json" and "write_json" in Yosys | 15:53 |
| daveshah | this is the current recommended interface for external tools working with Yosys | 15:53 |
| azzizi_ | read_json converts a verilog source code into json ? and write_json converts json to verilog netlist? | 15:55 |
| ZipCPU | No. | 15:56 |
| ZipCPU | write_json converts the internal representation to a JSON output file. | 15:56 |
| ZipCPU | read_json reads the given JSON file and initializes the internal structures with the information found within it. | 15:56 |
| ZipCPU | Neither file translator works on Verilog. Verilog may however be ingested into yosys, and then converted to JSON. | 15:57 |
| azzizi_ | <ZipCpu> By ingested, do you mean using read_verilog and then write_json | 16:01 |
| ZipCPU | Pretty much, plus any transformations that have taken place in between. | 16:01 |
| azzizi_ | <ZipCpu> Can I go back from json to verilog netlist.... like read_json and then write_verilog? | 16:03 |
| ZipCPU | It'll be just like it was when you tried read_verilog followed by write_verilog. The result might look nothing like the input, although it should be logically equivalent | 16:04 |
| azzizi_ | Basically I want to modify an intermediate representation ....add some stuffs an then input the modified representation into Yosys | 16:04 |
| ZipCPU | You are likely to find JSON useful for that purpose. | 16:06 |
| azzizi_ | JavaScript Object Notation? | 16:06 |
| ZipCPU | Is that what JSON stands for? | 16:07 |
| azzizi_ | yeah I googled | 16:07 |
| azzizi_ | Am I right ? I wish the RTLIL were stable lol | 16:08 |
| azzizi_ | Wouldn't have to look into JSON any more | 16:08 |
| ZipCPU | I just refactored yosys's JSON parser into another piece of software for another purpose. It wasn't really all that hard. | 16:09 |
| azzizi_ | In the manual I dont see any read_json | 16:17 |
| azzizi_ | read_json reads the given JSON file and initializes the internal structures with the information found within it. | 16:21 |
| azzizi_ | so can I assume it transforms Json format to RTLIL? | 16:21 |
| azzizi_ | Sorry for asking too many questions lol | 16:23 |
| ZipCPU | Yes, you may assume that. | 16:28 |
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| azzizi_ | I have seen the JSON format, but it seems it doesn't have all the information flow there unless I am mistaken..netlist information is there ..but not the data flow | 17:26 |
| azzizi_ | Anyone? | 17:54 |
| awygle | i'm not sure what you mean by data flow in this context | 17:54 |
| azzizi_ | https://imgur.com/a/xs167on | 17:56 |
| tpb | Title: Help please - Album on Imgur (at imgur.com) | 17:56 |
| azzizi_ | For this source code, data flow would be the lines state<=1 and stuffs like that | 17:57 |
| azzizi_ | I converted the RTLIL to json | 17:57 |
| azzizi_ | But not being able to find the JSON lines representing the dataflows | 17:58 |
| azzizi_ | Please help | 18:06 |
| ZipCPU | azzizi_: What do you mean by "data flow"? What specifically are you looking for? | 18:06 |
| ZipCPU | Oh, yeah, one more thing azzizi_: Look at the *last* main element in the JSON file to find your logic. | 18:07 |
| ZipCPU | With the JSON file's I've looked to date, the other items don't describe your logic, but often rather the capabilities of the elements in your system. | 18:07 |
| azzizi_ | So are you saying not all the information will be there in Json file ? | 18:08 |
| azzizi_ | I am pretty sure RTLIL has everything ...but if JSON doesnt have everything I have no other options but to work on RTLIL but as this is not stable I am in a dilemma | 18:09 |
| ZipCPU | No, the other way around: you may have more information in the JSON file than just your design. | 18:09 |
| daveshah | azzizi_: the JSON file contains an elaborated version of your design | 18:10 |
| daveshah | You might want to run proc or even prep before generating it | 18:10 |
| daveshah | Then the data flow should be included, albeit converted to a netlist | 18:10 |
| azzizi_ | http://textuploader.com/dza0z | 18:12 |
| tpb | Title: 'Please see' | TextUploader.com (at textuploader.com) | 18:12 |
| azzizi_ | Please check this Json output ...no dataflow | 18:13 |
| azzizi_ | the source code for the previous imgur | 18:13 |
| daveshah | azzizi_: run `proc` before generating the json | 18:15 |
| daveshah | you can already see the add and equals cells. Other cells for the registers etc will be created when you run `proc` | 18:15 |
| azzizi_ | Thanks it worked now ...but sadly it is at the netlist level ..with the mux and registers added which I don't want ...I need to be able to edit the code at higher level than that ...changing the RTLIL would be perfect for me | 18:19 |
| azzizi_ | But it may change in future and not stable so Ihave to rethink some stuff | 18:19 |
| daveshah | Yeah, in practice it sounds like RTLIL will be OK. I doubt there will be any breaking changes, but its also not really guaranteed | 18:21 |
| azzizi_ | what is not guaranteed ? | 18:21 |
| daveshah | That RTLIL Ilang will be a stable interface forever | 18:22 |
| daveshah | But it's almost certainly fine. Officially though that kind of stuff should be done using the C++ interface directly | 18:23 |
| azzizi_ | Thanks, May I know if you know of any ways to input the modified RTLIL (that I get from the script I will write) into the Yosys steps so I can work with it in the latter steps of yosys ....like with the new RTLIL in the Yosys ...if I write write_verilog then it will give me verilog netlist | 18:24 |
| daveshah | Yes, use read_ilang | 18:24 |
| azzizi_ | Why not read_rtlil ? | 18:29 |
| azzizi_ | Sorry just asking | 18:29 |
| azzizi_ | I thought ilang was a textual representation of rtlil so they must be the same thing | 18:29 |
| daveshah | RTLIL is the name for the internal data structures representing RTL. "ilang" is the name when it is dumped in textual form | 18:30 |
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| azzizi_ | SO in the picture shown in the manual, it is depicted we can work on RTLIL ...by writing any pass not ILANG | 18:51 |
| azzizi_ | So the modified RTLIL has to be in ilang form for me to be using the read_ilang command? | 18:54 |
| daveshah | I don't understand your question | 18:55 |
| daveshah | ilang is the only external direct form of RTLIL | 18:55 |
| azzizi_ | https://imgur.com/a/DfPm8r4 | 19:09 |
| tpb | Title: Help - Album on Imgur (at imgur.com) | 19:09 |
| azzizi_ | The picture shows passes work on RTLIL ...so it has all the information...I know I can get the RTLIL form of any source code by read_verilog -dump rtlil ................but if I want to do the reverse ...my script will modify rtlil and input the modified RTLIL into yosys I can't use read_rtlil or something like that ? | 19:13 |
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| azzizi_ | Why do I have to work with ilang | 19:14 |
| daveshah | RTLIL is the name for the external data structures. If you want to work with RTLIL directly, use the C++ interface. Otherwise ilang is the text form of RTLIL for external use | 19:15 |
| azzizi_ | May I ask the commands for the commands for getting Ilang representations of any verilog? and also Ilang to verilog netlist? | 19:18 |
| azzizi_ | Thanks ...the last sentence explained a lot | 19:18 |
| daveshah | read_verilog x.v; write_ilang x.ilang | 19:19 |
| daveshah | read_ilang x.ilang; proc; write_verilog x.v | 19:19 |
| daveshah | The proc may or not be needed in the latter case | 19:19 |
| azzizi_ | Depending on if I use 'always' ? | 19:20 |
| daveshah | Yeap | 19:20 |
| azzizi_ | Thanks a lot | 19:20 |
| daveshah | Sometimes it will work directly with write_verilog | 19:20 |
| daveshah | But proc is safer | 19:20 |
| azzizi_ | proc seems to take everything in the netlist level though ...adds mux and registers ..too low a level to work for me | 19:21 |
| azzizi_ | although I have not seen | 19:21 |
| azzizi_ | yet | 19:21 |
| daveshah | azzizi_: I am curious, what exactly are you trying to do that must be done at Verilog source level rather than on an elaborated netlist? | 19:44 |
| azzizi_ | <daveshah> It's an amendment of some sort of the source information so as to not let the IP attackers lives be more difficult | 19:50 |
| azzizi_ | let the * | 19:50 |
| azzizi_ | lol | 19:50 |
| daveshah | azzizi_: sounds very interesting | 19:50 |
| azzizi_ | yeah it is ...thanks | 19:51 |
| daveshah | I know there are some people doing this kind of research with Yosys. Might be worth getting in touch with them? | 19:51 |
| daveshah | I think Christian Krieg at TU Vienna is one of them | 19:52 |
| azzizi_ | May I ask how do I contact him ? | 20:04 |
| azzizi_ | That would be of great help | 20:04 |
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| daveshah | Don't have contact details I'm afraid. But his Twitter is https://twitter.com/_christiankrieg | 20:06 |
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| azzizi_ | Anyone has any verilog code for which Ilang and rtlil is different ? for me allof my example codes RTLIL and Ilang are same | 21:05 |
| daveshah | azzizi_: I am not sure if they will ever be different, ilang is the text representation of RTLIL, the only difference is in the naming of the command generating the output | 21:07 |
| azzizi_ | Thanks again deveshah | 21:10 |
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