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| promach_ | hi guys, using $past(variable) on the condition for assert(variable) is not helpful for yosys-smtbmc temporal induction, right ? | 15:34 |
|---|---|---|
| promach_ | https://github.com/promach/UART/blob/development/rtl/test_UART.v#L141-L152 | 15:34 |
| tpb | Title: UART/test_UART.v at development · promach/UART · GitHub (at github.com) | 15:35 |
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| ZipCPU | No, promach_: it should be just find for induction. | 15:55 |
| promach_ | ZipCPU: but I really doubt, because $past(variable) could be of anything in induction, right ? | 15:56 |
| ZipCPU | The only issues are that it will only work in a clocked always block, the "erroneous" trace will appear on the second to the last clock, and who knows what past references on the very first time step during induction. | 15:57 |
| ZipCPU | (You'll have to recover from that first timestep in the following time steps) | 15:57 |
| promach_ | ZipCPU: but I am using $past(variable) on the condition for assert(variable) in induction | 16:13 |
| ZipCPU | Yes, that was what I thought I was talking about. | 16:13 |
| ZipCPU | I do it all the time. | 16:14 |
| promach_ | hmm... probably I should look for the induction bug at some other place in my code then | 16:14 |
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| azzizi | Hi can anyone please tell me if the 'passes' can be written in python ? or using c++ is a must? | 18:01 |
| azzizi | To clarify passes on the RTLIL | 18:01 |
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| ZipCPU | azzizi: I would imagine they could be written in Python, don't see why not, however you might need to build your own patched infrastructure to make that happen. | 18:07 |
| azzizi | could you please elaborate on 'patched infrastructure' a bit more ? Not getting that | 18:09 |
| azzizi | e.g. i would like to add some things on the RTLIL suppose say with python ...what are the things to keep in mind | 18:10 |
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| ZipCPU | My point is specifically that the current infrastructure doesn't include python. You would need to connect your pythong code to yosys yourself. | 18:23 |
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