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| develonepi3 | Hello Bare Metal on the RPI programmed the CATBOARD. | 18:31 |
|---|---|---|
| develonepi3 | With speechfifo.bin Verilog provided by ZipCPU | 18:31 |
| develonepi3 | hen using the RPi uart Received data being sent from the HX8K FPGA. | 18:32 |
| develonepi3 | Bare Metal UDP Server sent the data to a host using a UDP socket. | 18:32 |
| develonepi3 | https://github.com/develone/Ultibo_Projects/blob/master/progcat/speechfifo.png | 18:33 |
| tpb | Title: Ultibo_Projects/speechfifo.png at master · develone/Ultibo_Projects · GitHub (at github.com) | 18:33 |
| develonepi3 | https://github.com/develone/Ultibo_Projects/blob/master/progcat/speechfifo.txt | 18:34 |
| tpb | Title: Ultibo_Projects/speechfifo.txt at master · develone/Ultibo_Projects · GitHub (at github.com) | 18:34 |
| develonepi3 | I have been trying to get FPGAs into Ultibo the bare metal project for the RPi, | 18:36 |
| develonepi3 | With the cmd tftp xx.xx.xx.xx < cmdstftp a new program can installed in the FPGA. | 18:42 |
| develonepi3 | The RPi reboots when the new kernel7.img is received. | 18:43 |
| develonepi3 | I now have 13 projects that can be updated by the same method. | 18:46 |
| develonepi3 | The jpeg project demonstrates using C with bare metal. I have compiled openjpeg to a static lib and is now works on bare metal. | 18:52 |
| develonepi3 | yosys tools & bare metal will make a great combo. | 18:53 |
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