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| ZipCPU | The context: Someone on the ##dsp channel was asking about the utility of a breviaXP2 | 00:03 |
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| ZipCPU | I was wondering if that FPGA, which I wasn't familiar with, was also supported by #yosys ... since I don't think all that much about Lattice Diamond | 00:03 |
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| GuzTech | Hey guys, in case you are interested... | 16:19 |
| GuzTech | Part 2 of my Clash tutorial is out: https://bitlog.it/hardware/a-basic-introduction-to-clash-for-fpga-development-part-2/ | 16:19 |
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| ZipCPU | o/ | 16:32 |
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| keesj | After today I will write everything using magic VLSI http://opencircuitdesign.com/magic/ such cool project to create your own ic http://sam.zeloof.xyz/first-ic/ | 17:06 |
| tpb | Title: Magic VLSI (at opencircuitdesign.com) | 17:06 |
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| emeb | Uh... yeah. So simple - a child could do it. https://www.youtube.com/watch?v=dDs71u-KAME | 20:32 |
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| emeb | And of course, there's the whole problem of actually getting an IC made for a reasonable cost. | 20:33 |
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| shapr | emeb: https://mobile.twitter.com/onchipUIS/status/988467731342200834 | 20:34 |
| tpb | Title: Twitter (at mobile.twitter.com) | 20:34 |
| emeb | shapr: yes, but... | 20:35 |
| emeb | with that process for $100 you get: 1/64th of the whole chip, no I/O pads and shared SPI / JTAG ports. | 20:35 |
| shapr | yeh, true | 20:35 |
| sorear | How much do you pay for process info/ tools? | 20:46 |
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