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| mithro | So, I don't understand when I should use "prep" and when I should use "synth" in yosys? | 00:14 |
|---|---|---|
| ZipCPU | mithro: prep for formal | 00:16 |
| ZipCPU | let me check a bit deeper tho | 00:16 |
| mithro | Should the following describe a 4 input, 1 output lut? | 00:17 |
| mithro | https://www.irccloud.com/pastebin/GNF75eHj/ | 00:17 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 00:17 |
| ZipCPU | Sure looks like it! | 00:18 |
| ZipCPU | You might wish to notice, though, that prep doesn't read in any cell libraries | 00:18 |
| ZipCPU | As a result, if you run prep on that you probably won't get a 4-input LUT | 00:18 |
| mithro | So, yosys seems to outputting the following blif file | 00:18 |
| mithro | https://www.irccloud.com/pastebin/fMKdHfsI/ | 00:19 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 00:19 |
| mithro | ZipCPU: I'm using synth at the moment... | 00:19 |
| ZipCPU | What architecture are you trying to target? | 00:20 |
| mithro | yosys -p "synth; abc -lut 4 opt_clean; write_blif -attr -cname -conn -impltf -param build/testarch/2x4/vlut.eblif" vlut.v | 00:20 |
| ZipCPU | What architecture are you trying to target? | 00:20 |
| mithro | A test architecture that doesn't really exist.... | 00:20 |
| mithro | Any idea why the missing semicolon between abc and opt_clean didn't cause yosys to error? | 00:21 |
| ZipCPU | Because opt_clean was taken to be an argument to abc | 00:21 |
| mithro | ZipCPU: yosys doesn't check args passed to abc and/or abc doesn't error on the opt_clean extra argument? | 00:22 |
| ZipCPU | that follows from your description, does it not? I haven't checked the yosys code, and you've got the log file. | 00:23 |
| mithro | Yeah - it seems so | 00:23 |
| mithro | Just testing more now | 00:23 |
| ZipCPU | I was at one time surprised when clifford explained to me what opt -share_all did. It called the "opt" process and applied it to "-share_all" portion of my design | 00:25 |
| ZipCPU | I had been using it in all my designs up to that point. | 00:25 |
| ZipCPU | Oops | 00:26 |
| mithro | ZipCPU: https://github.com/YosysHQ/yosys/issues/532 | 00:31 |
| mithro | ZipCPU: Now I have the semicolon things seem to work... I'm getting a single 4 input lut... | 00:32 |
| ZipCPU | ;) | 00:32 |
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| mithro | Hrm, yosys isn't generating the .attr and .param values I'd expect... | 00:42 |
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| awygle | mithro: there's a flag to generate .attr and .param compatible with arachne | 01:24 |
| awygle | Is that what you're expecting? | 01:24 |
| mithro | awygle: Yeah -- using the http://www.clifford.at/yosys/cmd_write_blif.html | 01:26 |
| tpb | Title: Yosys Open SYnthesis Suite :: Command Reference :: write_blif (at www.clifford.at) | 01:26 |
| mithro | write_blif -attr -cname -conn -impltf -param out.eblif | 01:27 |
| awygle | Hmm OK you're already using attr and param | 01:28 |
| mithro | awygle: I'm getting .conn - so some part of it is working... | 01:28 |
| mithro | awygle: Ahh - it seems to only set .attr on .subckt -- not on .names and .latches ..... | 01:33 |
| awygle | Ahh | 01:33 |
| mithro | awygle: https://github.com/YosysHQ/yosys/issues/533 | 01:46 |
| tpb | Title: When should yosys be generating extended eblif attributes? · Issue #533 · YosysHQ/yosys · GitHub (at github.com) | 01:46 |
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| keesj | https://www.crowdsupply.com/tinyfpga/tinyfpga-bx/updates/tinyfpga-b2-and-bx-projects so cool | 08:09 |
| tpb | Title: TinyFPGA BX - TinyFPGA B2 and BX Projects! | Crowd Supply (at www.crowdsupply.com) | 08:09 |
| keesj | https://www.crowdsupply.com/rhs-research/picoevb also | 08:12 |
| tpb | Title: PicoEVB | Crowd Supply (at www.crowdsupply.com) | 08:12 |
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| tito_ | hi | 14:51 |
| janrinze | hi | 14:51 |
| tito_ | help to use Diamond FPGA, I posse ice40 1k stick , i'm nabbo I can not create projects, and I have to insert fail to do vga ....... link for me | 14:55 |
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| tito_ | help to use Diamond FPGA, I posse ice40 1k stick , i'm nabbo I can not create projects, and I have to insert fail to do vga ....... link for me | 16:14 |
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| mazzoo | hello | 16:15 |
| mazzoo | I'm playing with picosoc and some firmware... | 16:15 |
| mazzoo | this works nicely: https://pastebin.com/0v8fWRu8 | 16:15 |
| tpb | Title: [C] // -------------------------------------------------------- #define LEN_HEART - Pastebin.com (at pastebin.com) | 16:15 |
| mazzoo | (it's a simple POV heart) but I can't declare the sign_heart outside of the function | 16:16 |
| mazzoo | even as static it won't work | 16:16 |
| mazzoo | what am I missing? | 16:16 |
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| tito_ | hi help to use Diamond FPGA, I posse ice40 1k stick , i'm nabbo I can not create projects, and I have to insert fail to do vga ....... link for me | 16:42 |
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| ZipCPU | tito_: You asked a week ago. You claimed to be a newbie, and were trying to place projects (not even built ones) on boards for which they weren't designed. | 16:55 |
| ZipCPU | Further, you were unwilling to learn how to do a design in order to make those projects fit. | 16:55 |
| ZipCPU | I'm not sure how I could help you at this point. | 16:55 |
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| tito_ | I'm not able to make drawings, I'm not even able to open projects, I can not use the programs for fpga, I have an usb ice40 and I have to turn it into vga, I need links, to upload files and I do not understand | 17:02 |
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| ZipCPU | You may have to explain some more: why can't you make any drawings? and how do you intend to turn an ice-stick into an VGA, if it doesn't have a VGA connector on it? | 17:23 |
| ZipCPU | Opening projects I can teach, but not if you have no willingness to learn. | 17:23 |
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| shapr | yay chicago adventures! | 17:24 |
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| sorear | Oh? | 17:38 |
| tito_ | I understand only that a usbstick can be programmed and transformed into vga. I do not know any other problems like pins or connectors. I bought an economic ice40 having files, to try ..... but having the files I was hoping not to have problems, to open the program and copy to fpga, now I think it is not possible to transfer fpga files in a simple way as an open / save. | 17:40 |
| daveshah | tito_: What VGA files were you expecting to try? | 17:41 |
| ZipCPU | tito_: You might've had more success if you purchased the same FPGA that was used in the VGA demo project you were looking at: a Spartan 6 (I'd have to look up which one). Most Spartan 6's have a lot more resources than an iCE40. | 17:49 |
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| ZipCPU | It may not even be possible to place a Spartan 6 design onto an iCE40 -- especially not a 1k iCE40, but then again ... there are designs that will fit. | 17:50 |
| mazzoo | BTW: does a picorv32 together with a (e.g.) SimpleVOut fit on an 8k iCE40? | 17:57 |
| knielsen | probably; I remember putting picorv32 on an 8k along with some simple support logic, taking ~ 50% of luts | 17:59 |
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| sorear | shapr: Chicago? | 18:03 |
| shapr | sorear: yup, are you in chicago? | 18:11 |
| shapr | sorear: if yes, want to hang out and chat this evening? | 18:11 |
| sorear | shapr: unfortunately no | 18:11 |
| sorear | shapr: i'm in Boston rn; forget if I ever told this channel | 18:12 |
| sorear | [was asking what the chicago adventures were] | 18:12 |
| tito_ | I also found https://github.com/lattice/quda but the problem is always that they are files ........ and I can not find guides to transfer and I do not understand. I can not even talk to ice ........ | 18:14 |
| tpb | Title: GitHub - lattice/quda: QUDA is a library for performing calculations in lattice QCD on GPUs. (at github.com) | 18:14 |
| shapr | sorear: oh, I'm giving a Haskell intro at the south side hackerspace chicago | 18:14 |
| sorear | [incidentally if anyone here IS in the greater MIT area…] | 18:15 |
| shapr | sorear: I would have looked you up this past November if I'd known that | 18:16 |
| sorear | shapr: i've been here three weeks, before that I was in San Diego | 18:17 |
| shapr | oh | 18:18 |
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| tito_ | hi | 23:11 |
| tito_ | I would have 1 question | 23:12 |
| mithro | Clifford was interested in posits IIRC? | 23:21 |
| mithro | Does anyone know why this set of -luts arguments was chosen for Xilinx Synth ? --> abc -luts 2:2,3,6:5,10,20 | 23:27 |
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