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| philtor | ZipCPU, did you do a writeup on this HITL testing methodology? That would be an interesting read. | 01:03 |
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| ZipCPU | philtor: Not specifically, but I think I might have mentioned it in the FFT article, | 01:35 |
| ZipCPU | ... let me check ... | 01:45 |
| philtor | It would make a great blog post :) | 01:48 |
| ZipCPU | http://zipcpu.com/digilent/2017/05/29/fft-debugging.html | 01:53 |
| tpb | Title: FFT debugging (at zipcpu.com) | 01:53 |
| ZipCPU | Yeah, so ... you can read the post if you like, or I can tell you the story ... :) | 01:53 |
| ZipCPU | The story goes back to a dark man, with a dark purpose, waiting on a dark night ... Oops, sorry, that's Aladdin ... let me try again ... | 01:54 |
| ZipCPU | No, seriously, I was programming my very first FPGA. The hardware engineer had delivered me a circuit board. The Linux engineer had placed a Linux distro on the ARM chip on that board. The FPGA was connected via an auxiliary bus to the ARM chip. | 01:55 |
| ZipCPU | The hardware engineer who had "proved" that the board worked, gave it to me empty with only one configuration on it--one that allowed the reading from or writing to bus addresses. | 01:56 |
| ZipCPU | Hence, from the Linux program I could read from a memory-mapped address within the FPGA. | 01:56 |
| ZipCPU | My first program mapped a 3-bit input from an offset A/D into a 4'bit value that would properly handle the task. I tested it via writing the value to the bus, and reading the result back off. | 01:57 |
| ZipCPU | I managed to use that same basic interface to build a GPS front-end processing system, and again to build a custom radio system. | 01:58 |
| ZipCPU | The custom radio was fascinating, since I would write to a "clock register" that would step the entire design. I could then come back and read information back off at my convenience, one word per clock. | 01:58 |
| ZipCPU | I'd write the "input" from the antenna (i.e. simulation) into one register, and then watch as it cascaded through the processing chain. | 01:59 |
| ZipCPU | On the whole, I found the technique quite useful at the time. | 01:59 |
| ZipCPU | In hind sight, I might've moved through the project faster if I had used simuation--since it would take ISE (Spartan 3) about 15 minutes to build each test design, and I can often simulate something in less than a minute or two. | 02:00 |
| ZipCPU | When I had to stop stepping the design, it was as easy as setting that step register field to a 1'b1, and all the debugging code would be optimized out of the design. | 02:01 |
| ZipCPU | When I switched to full speed, I had two problems. The first I solved with the predecessor of the wishbone scope, creating something like a chipscope capability. The other was the fact that ... my simulated radio matched the receiver clock perfectly. Oops. Reality was a touch more difficult. | 02:02 |
| ZipCPU | The funny part was the response of the veteran FPGA designers watching me with my first design. In general, they just shook their heads in dismay. When I delivered, they then scratched their heads somewhat. Either way, the approach was an anomaly. | 02:03 |
| ZipCPU | philtor: That's the basic story. | 02:04 |
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| keesj | ZipCPU: I now better uderstand why you asked about my serial to register mapping project. | 05:25 |
| keesj | I never user chipscope so far (i remember scanning some jtag scan chain but somewhere I must have run into problems) This was on a Digilen Basys2 Xilinx Spartan-3E FPGA. | 05:28 |
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| promach__ | for the smt_step, how do I reference it in assert() ? | 16:25 |
| ZipCPU | promach__: Give me a little more back ground ... what are you talking about? | 16:28 |
| promach__ | ZipCPU: I am trying to assert a relationship between 'cnt' and 'state' as in https://i.imgur.com/nc4T8jC.png | 16:30 |
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| ZipCPU | Ah ... to my knowledge, you don't reference the smt_step number in an assertion. You can create your own counter to reference if you would like, but you can't reference that one. | 16:32 |
| promach__ | ok, I see. Thanks | 16:32 |
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