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| janrinze | ZipCPU: i noticed that the ZipCPU should be able to run at 40MHz on the IcoBoard. The timings for my own cpu design show that 16x16 multiply is around 40 ns. how did you manage 32 bit at 40 MHz? | 10:19 |
|---|---|---|
| ravenexp | not all cpus do mul in a single cycle | 11:06 |
| ravenexp | well, most don't | 11:06 |
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| ZipCPU | The ZipCPU will do a multiply in 1-4 cycles, depending on how you set up the code. 7-series can usually do 3 cycles IIRC, Spartan 6's require 4. | 11:16 |
| ZipCPU | The iCE40 design can't handle either, so the multiply instruction is an illegal instruction on that design. | 11:16 |
| ZipCPU | I'm hoping to trap it and replace it with a soft multiply ... I just haven't gotten that far. | 11:17 |
| ravenexp | ZipCPU: are you using DSP macros in xilinx? | 11:18 |
| ZipCPU | DSP's yes, macros no. | 11:18 |
| ZipCPU | You can check out this portion of the design if you want. It's (currently) in https://github.com/ZipCPU/zipcpu/blob/master/rtl/cpu/cpuops.v | 11:19 |
| ZipCPU | There's a large section there that handles multiplies. | 11:19 |
| ZipCPU | I'm in the process of pulling this out into its own file, but ... that's where it's at currently. | 11:20 |
| ravenexp | I get 404 | 11:20 |
| ZipCPU | Ah, let me try again ... https://github.com/ZipCPU/zipcpu/blob/master/rtl/core/cpuops.v | 11:20 |
| tpb | Title: zipcpu/cpuops.v at master · ZipCPU/zipcpu · GitHub (at github.com) | 11:20 |
| ravenexp | and now it works | 11:22 |
| ZipCPU | On the iCE40 the OPT_MULTIPLY option is set to zero, bypassing the multiply code | 11:23 |
| ravenexp | is xst able to make sense of this? | 11:25 |
| ravenexp | like infer 18x18 multipliers the dsp blocks have? | 11:26 |
| ZipCPU | xst uses the last one, and yes it can make sense of it | 11:26 |
| ravenexp | if I were making a soft CPU, I'd implement 18x18 muls in the hard blocks, and trap on anything larger | 11:28 |
| ravenexp | because I hate programmers | 11:28 |
| ravenexp | no hw division for them, either | 11:28 |
| janrinze | ZipCPU: Thanks for the clarification. | 11:28 |
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| ZipCPU | Oh, and as for the 40MHz ... the CPU will need to run at 50MHz on the icoBoard I'm running it on, and it can actually make that number. | 11:30 |
| ZipCPU | 40 is a leftover from trying to find a bug, and it won't work with the SRAM on the icoBoard--something I haven't added to the design yet. | 11:31 |
| ravenexp | I wonder how many prorammers even know that bits [63:32] of the result exist | 11:31 |
| janrinze | ZipCPU: i can only manage around 33 MHz with my own CPU design.. | 11:32 |
| janrinze | ZipCPU: is that number with using a cache? | 11:32 |
| ZipCPU | ravenexp: GCC knows. | 11:32 |
| ZipCPU | Couldn't fit the cache on the icoBoard | 11:33 |
| ZipCPU | Although ... the cache is one of my faster components--will run at 200MHz on a series 7, even though the ALU slows me down to 100 or so | 11:33 |
| janrinze | Okay, so no cache.. I have the memory shared between vga and cpu so that limits the bandwidth a bit to SRAM. | 11:34 |
| ravenexp | there's been exactly 0 times I saw our programmers doing anything other than 32x32->32 muls or even bothering to check for overflow | 11:34 |
| ZipCPU | Library code requires 64-bit support. | 11:34 |
| ravenexp | that could be handled with software emulation like divisions | 11:35 |
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| ZipCPU | I suppose | 12:24 |
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| janrinze | ZipCPU: How did you get a compiler for your CPU? | 18:53 |
| ZipCPU | I used GCC, and built the backend myself. | 18:54 |
| janrinze | ZipCPU: I resorted to writing my own compiler.. hope that the target system will be able to compile code for itself.. | 18:54 |
| janrinze | ZipCPU: using gcc implicitly imposes a lot of things to be supported by the cpu, right? | 18:55 |
| ZipCPU | Such as ...? | 18:55 |
| janrinze | okay.. perhaps i was mistaken there. | 18:57 |
| janrinze | i've only built a 16 bit cpu which does not have many instructions. | 18:57 |
| ZipCPU | GCC supports other 16-bit architectures. | 18:58 |
| janrinze | 16 bit pointers.. | 18:58 |
| ZipCPU | I'll also point out, I needed to change the ISA to get linking to work ... ;) | 18:58 |
| janrinze | so max 64KB range. | 18:58 |
| ZipCPU | Sure! | 18:58 |
| ZipCPU | The ZipCPU originally supported only 32-bit bytes. Getting that to work with GCC was my first success. | 18:59 |
| ZipCPU | It now supports 8-bit bytes, so GCC support is a bit simpler. | 18:59 |
| janrinze | 16 bit bytes here :-) | 18:59 |
| qu1j0t3 | ZipCPU: did you do a writeup on the gcc backend? | 18:59 |
| ZipCPU | No, not yet. I've wanted to. It's on my to do list. I'm just not quite certain how to dip into it without going into it whole hog--if you know what I mean. | 19:00 |
| awygle | happy easter, ZipCPU | 19:01 |
| qu1j0t3 | yeah, i'm sure it's a big project. a lot of people would benefit though | 19:01 |
| ZipCPU | The other problem is ... I'm not sure to what extent an FPGA programmer would want to dive into GCC internals. CPU designers, definitely, general FPGA designers? I'm not certain. | 19:02 |
| ZipCPU | awygle: Happy resurrection day! Thank you, awygle. http://zipcpu.com/bog/2018/04/01/resurrection-day.html ! | 19:02 |
| qu1j0t3 | people doing backends for historical cpus are definitely out there | 19:02 |
| janrinze | yup. understand that. | 19:02 |
| awygle | janrinze: the msp430 backend is actively supported and that's a 16-bit architecture (except when it's 20-bit but never mind) | 19:03 |
| ZipCPU | Also ... I think I want to merge the ZipCPU into GCC mainline. That means I need to go into binutils mainline first, and in particular I'll need to clean up my assembler backend ... lots of work. | 19:03 |
| janrinze | hence i resorted to writing my own compiler. I was able to write that in 2 weeks. I doubt i could finish reading up on gcc internals in two weeks.. | 19:03 |
| ZipCPU | It took me about 2-3 months to build a GCC backend. | 19:03 |
| qu1j0t3 | ZipCPU: that would be really nice, but will they merge it? They have been known to yank real, important cpus | 19:03 |
| ZipCPU | Then another 2-months to rewrite it for 8-bit bytes ... | 19:04 |
| ZipCPU | qu1j0t3: Good question. Not sure I really know the answer. It'd be nice to know. | 19:04 |
| ZipCPU | I guess all I can do is ask when I get to that point. | 19:04 |
| janrinze | ZipCPU: with gcc it means that C++ can be used too? | 19:04 |
| ZipCPU | Basically, although I don't really have a good and thorough test suite to know. | 19:05 |
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| ZipCPU | I mean ... the back end I've built should theoretically support every front end. However, I haven't tested them all, and each front end uses the back end differently so ... | 19:06 |
| ZipCPU | Let me try things this way ... you are invited to experiment with the ZipCPU's back end and your favorite language. If it doesn't work, let me know and we can look at it together. :D | 19:07 |
| janrinze | If i can find time to look at the ZipCPU then I will let you know. For now I am indulging myself in this whole computer-from-scratch experience. ;-) | 19:08 |
| ZipCPU | janrinze: Enjoy! You might argue that the ZipCPU was just exactly that from my perspective. There's a *lot* of road, though, between the drawing board and playing 4x4x4 tic-tac-toe using the C-library. | 19:09 |
| janrinze | yes. I am now doing some graphics demos as test bench | 19:10 |
| ZipCPU | Did you find my VGA simulator at all? | 19:10 |
| ZipCPU | It's more of a display simulator than a VGA simulator ... but I named it a VGA simulator, and the name has held. | 19:10 |
| janrinze | I started with an Acorn Atom in-a-fpga some two years ago. | 19:11 |
| awygle | Ada-on-ZipCPU | 19:11 |
| janrinze | so i could easily swap the 6502 cpu there with a new cpu. | 19:11 |
| ZipCPU | :D | 19:11 |
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| ZipCPU | awygle: Are you just trying to get me started? :P | 19:11 |
| ZipCPU | janrinze: There was a wonderful O/S text on OpenCores. When I wrote to the author to tell him how much I loved reading through it, he said that though he had built his own ISA for his CPU at first, he stopped doing it. | 19:12 |
| ZipCPU | There was just too much work involved in maintaining the port of the tools | 19:12 |
| janrinze | oh, but of course. | 19:13 |
| awygle | ZipCPU: get you started learning ada so you can help get ghdl support into yosys? maybe. | 19:13 |
| ZipCPU | awygle: Would you believe that I originally wrote the F-16 flight sim for my masters degree thesis in Ada? | 19:13 |
| janrinze | technically a 64K-word system won't run much stuff you can grab in c-sources. | 19:14 |
| ZipCPU | janrinze: There was also a fascinating comment in the GCC soft FPU emulation code: "Here's a quarter kid, go get yourself a real CPU" | 19:15 |
| ZipCPU | This was the error message if you tried to compile the FPU emulation on a machine that didn't support 4-byte integers. | 19:15 |
| janrinze | true that.. even a cortex M-0 does not have FPU.. | 19:15 |
| janrinze | back in '97 we could hardly get gcc to produce code for the ARM without doing some inline assembly to fixup things.. | 19:19 |
| janrinze | the ARM sprouted from the legacy Acorn Atom and it's siblings. so to me this is sort of a walk through alternative time line. ;-) | 19:22 |
| janrinze | ZipCPU: have you tried the ulp5K yet? | 19:31 |
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| ZipCPU | janrinze: Nope, not yet | 20:30 |
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