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| dmin7 | hi, i wonder, has anyone ever done anything with icosoc raspi interface besides using it to write debug output? (reading data from it eg x) | 08:45 |
|---|---|---|
| dmin7 | or the SPI that is used for flashing from within C code .. | 09:01 |
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| ZipCPU | Yes, dmin7, I've built the parallel port into a full bidirectional interface with a TCP/IP redirect | 09:26 |
| dmin7 | oh, nice .. is there some code i can look at? | 09:30 |
| ZipCPU | It's in https://github.com/ZipCPU/icozip | 09:41 |
| tpb | Title: GitHub - ZipCPU/icozip: A ZipCPU demonstration port for the icoboard (at github.com) | 09:41 |
| ZipCPU | There's several parts to the interface. The FPGA side is kept in rtl/pport IIRC | 09:42 |
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| ZipCPU | The pport->TCP/IP bounce takes place in sw/host/netpport | 09:43 |
| ZipCPU | Programs using the interface would look something like the sw/host/wbregs program, and follow the interface in sw/host/devbus.h | 09:44 |
| dmin7 | i was affraid you were gonna say that (: .. i'm (still) using the picorv32/icosoc setup .. and as far as i can see your icozip doesn't have much to do with "icosoc"? | 09:46 |
| xerpi | shouldn't typedefs be allowed outside of modules? | 09:50 |
| xerpi | syntax error, unexpected TOK_TYPEDEF, expecting TOK_LOCALPARAM or TOK_ENDPACKAGE | 09:50 |
| xerpi | I have a typedef inside a package and outside of a module | 09:50 |
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| ZipCPU | dmin7: Ahh, I'm sorry, I missed that part of your question. :( | 09:52 |
| ZipCPU | xerpi: In Verilog? Does yosys even support that? | 09:53 |
| xerpi | ZipCPU, SystemVerilog | 09:53 |
| ZipCPU | I didn't think yosys had full sV support (yet) ... | 09:54 |
| xerpi | from the SystemVerilog standard "Types, nets, variables, tasks, functions, sequences, properties, and | 09:54 |
| xerpi | checkers may be declared within a package. " | 09:54 |
| xerpi | http://www.ece.uah.edu/~gaede/cpe526/2012%20System%20Verilog%20Language%20Reference%20Manual.pdf | 09:54 |
| xerpi | page 738 | 09:54 |
| xerpi | ZipCPU, yeah right | 09:55 |
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| ZipCPU | Well .. the front end does recognize the token, so ... there's at least something there ... | 09:55 |
| xerpi | I guess Verilog only allowed typedef inside of modules | 09:58 |
| dmin7 | ZipCPU: do you happen to have some instructions on howto get ICOZIP running (i'm using the icezero, not the icoboard, so i would have to adjust the pinout at least, i guess) | 10:02 |
| ZipCPU | Sadly, no. I spent so much time getting the pport interface to work, that I never managed to get the CPU up and running. | 10:04 |
| ZipCPU | Chief among the things to be done was the SRAM--I never managed to build the interface to it, or verify the code that uses that interface in simulation | 10:05 |
| ZipCPU | The SPI might need some work as well, and then the software "demos" | 10:06 |
| dmin7 | oh, ok, i guess i'll just try to get some sort of SPI working between the pi and icosoc then | 10:11 |
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| xerpi | is this a verilator bug or the standard? | 11:14 |
| xerpi | https://hastebin.com/raw/poxosafesa | 11:14 |
| xerpi | bar1 and bar2 have different values | 11:14 |
| xerpi | that's the full code: https://hastebin.com/raw/gayinosaju | 11:15 |
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| ZipCPU | xerpi: Have you looked through the code Verilator creates?? | 11:38 |
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| ZipCPU | Anyone interested in voting on the logo contest at: https://en.99designs.at/logo-design/contests/corporate-logo-evaluation-project-extended-cooperation-later-809088/poll/e9998dd703/vote?utm_source=voting_app&utm_medium=web&utm_campaign=voting | 18:50 |
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| mjo-uk_ | s/our toosl/our tools/ | 19:56 |
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