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| formalnewb | anyone around to help out? | 18:53 |
|---|---|---|
| daveshah | formalnewb: what do you need help with? | 18:54 |
| formalnewb | everything haha | 18:56 |
| formalnewb | i dont understand yosys/symbiyosys at all | 18:56 |
| formalnewb | i need help with intuition of it | 18:56 |
| formalnewb | can i paste what i've wrote out? | 18:56 |
| daveshah | formalnewb: sure | 18:56 |
| formalnewb | Im new to formal verification and formal property checking but I just started to learn to use OneSpin at work to prove assertions and covers but I wanted to know what else is out there if I wanted to do a hobby project with it. Obviously I can't afford a license for home use and I unfortunately can't use my business license at home for personal projects | 18:57 |
| formalnewb | I just learned about yosys/symbiyosys and was asking some questions about it in r/FPGA. According to the [latest documentation for symbiyosys](https://readthedocs.org/projects/symbiyosys/downloads/pdf/latest/) (published march 15, 2018) it lists sequences and implications from systemVerilog as a supported language feature. | 18:57 |
| formalnewb | But [a user on that thread I posted seemed to indicate that it wouldn't be supported unless I compiled my design with an expensive tool called Verific](https://www.reddit.com/r/FPGA/comments/851dwq/are_there_any_free_formal_tools_that_can_check/dvvwpiy). | 18:57 |
| tpb | Title: aseipp comments on Are there any free formal tools that can check System Verilog properties (assertions, covers, etc) (at www.reddit.com) | 18:57 |
| formalnewb | Does yosys/symbiyosys support assertions such as `req_sig |-> ##[1:5] grn_sig` without having an expensive tool like verific? | 18:57 |
| formalnewb | Can someone help me understand what exactly yosys and symbiyosys are and how I can use them for formal if I don't have access to Verific? I understand that Yosys is a synthesis tool that converts hdl code into primitives which another tool can use to build a bitstream to flash an fpga with. But what does that have to do with formal? SymbiYosys is described as a "front end driver" for Yosys but i don't really understand what that mea | 18:57 |
| formalnewb | Why does symbiyosys/yosys rely on a paid tool if it's trying to be a free and open source formal verification tool? Are these higher level formal constructs like `|->`, `s_until`, and sequences very difficult to get working? Excuse my ignorance i'm still a novice in formal. | 18:58 |
| formalnewb | thats it | 18:58 |
| formalnewb | sorry its a lot | 18:58 |
| thoughtpolice | formalnewb: I am that person in the reddit comment. | 18:58 |
| formalnewb | hahaha | 18:58 |
| daveshah | There's an awful lot of formal doable without SVA | 18:58 |
| formalnewb | well hello | 18:58 |
| daveshah | In fact it's probably the best place to start | 18:58 |
| daveshah | Have you seen ZipCPU's blog? http://zipcpu.com/ | 18:58 |
| tpb | Title: The ZipCPU by Gisselquist Technology (at zipcpu.com) | 18:58 |
| formalnewb | im sure, its just i learned formal with SVA so i just dont have a bearing on whas possible | 18:58 |
| formalnewb | i did look at the zipCPU | 18:59 |
| formalnewb | but the assertions he was doing werent very compelx | 18:59 |
| formalnewb | complex* | 18:59 |
| formalnewb | how would i mimic a sequence or an implication without SVA? | 18:59 |
| daveshah | Sure, I can see that. Clifford is working on all the backend code for SVA stuff, and all of that is open source already. Open source SVA support will exist, when parser and elaboration for it is written to replace Verific | 18:59 |
| daveshah | You can solve most problems just by writing simple state machines | 19:00 |
| daveshah | Or just using $past | 19:00 |
| formalnewb | can i ask a dumber question? | 19:00 |
| daveshah | Of course, I doubt it's dumb | 19:00 |
| thoughtpolice | formalnewb: To answer one of your questions, the relationship between SymbiYosys and Yosys is mostly what I said in that comment, but to be more complete: Yosys not only does things like converts HDL into a netlist for other tools (such as place and route), but it also does things like emit SMT problems, which is a major component of how its formal verification tools work. Yosys is really the bulk of the tooling, and is very much like | 19:00 |
| thoughtpolice | any synthesizer in another toolchain. | 19:00 |
| formalnewb | what is verific and what does it do that yosys cant do itself? I understand its a parser but i dont really know what that means | 19:00 |
| daveshah | Basically it is taking the SystemVerilog or VHDL code, processing it, and outputting a high level (not synthesised) netlist | 19:01 |
| formalnewb | i understand SAT because i took a course on theory of computation, but i never heard of SMT | 19:01 |
| thoughtpolice | For example, it has tcl support, it outputs technology mapped netlists, etc etc. SymbiYosys just adds a little bit of 'syntax sugar' on top to make it all a little nicer to use for the 95% of verification tooling you will actually do. | 19:01 |
| thoughtpolice | You don't have to use SymbiYosys at all. It's just convenient. | 19:02 |
| thoughtpolice | (Several people here don't use it, in fact. I do.) | 19:02 |
| formalnewb | so when you do formal what are you proving against? a netlist? | 19:02 |
| formalnewb | to me its just magic because OneSpin sort of does everything | 19:02 |
| formalnewb | i just write checker modules with a bunch of properties and assert statements and then bind the checker into my model | 19:03 |
| formalnewb | maybe i dont understand the toolchain process flow | 19:03 |
| daveshah | The toolchain flow, even with the open source tools, is very similar to a commercial tool with the SymbiYosys frontend | 19:04 |
| formalnewb | i mean i probably dont understand the toolchain flow for even commercial tools | 19:04 |
| formalnewb | in my understanding you have SystemVerilog code and it gets compiled (collecting all the files together, linking modules), then synthesized (converted to netlist of gates), then place and route for your specific FPGA, then a bistream is uploaded via JTAG to the fpga to program it | 19:05 |
| formalnewb | im not sure at which point you stop and go "im doing formal verification here" | 19:06 |
| daveshah | Yes, that's the standard FPGA flow | 19:06 |
| thoughtpolice | formalnewb: It's very close to that with Yosys, as well. You write a module with some properites, and then just blast it with the tooling. To be fair, the bit about SMT is more of an implementation detail, to be honest (which is interesting, but for the sake of clarity I was just trying to draw a distinction between the responsibilities of Yosys and something like Symbiyosys) | 19:06 |
| daveshah | In general formal flow stops a bit before synthesis | 19:06 |
| daveshah | You will do something similar to synthesis, but with a lot less optimisation. Whether you output gates (and/inverter graphs) or higher level blocks depends on the solver | 19:06 |
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| formalnewb | so yosys is a tool that compiles and synthesizes the code into some sort of lower level structures which can be used for formal verification | 19:07 |
| daveshah | Yes, exactly | 19:07 |
| thoughtpolice | Yes, exactly. And it can convert to netlists (and a bunch of other stuff) too | 19:07 |
| formalnewb | so what is verific doing? | 19:07 |
| daveshah | Verific is doing the initial interpretation and processing of SystemVerilog or VHDL | 19:08 |
| thoughtpolice | Yosys can only parse Verilog. Verific is just a software product, that gives you an API/library for parsing SystemVerilog/Verilog/VHDL. | 19:08 |
| daveshah | Dealing with all of the high level language constructs | 19:08 |
| daveshah | Exactly | 19:08 |
| thoughtpolice | The languages are all extremely complex, just Verilog alone is non-trivial. | 19:08 |
| formalnewb | ah so the folks at verific have made a tool that can understand all the structures that the systemverilog spec has said "we are going to offer these new cool things" | 19:08 |
| thoughtpolice | So Verific is sort of like, a stopgap, until there can be open source replacements for all of that. (Especially SystemVerilog) | 19:08 |
| thoughtpolice | Yosys has a fairly modular architecture, too, JFYI. So the open source Verilog frontend and Verific frontend can be used, both at the same time, if you have them both. They're both really just plugins; there are other input and output formats as well. | 19:10 |
| thoughtpolice | Yosys is sort of like a synthesis tool, and a verification tool, and a general piece of kit for working with RTL code. For example, I use yosys to 'beautify' auto-generated Verilog spit out by a compiler, because after beautifying it in certain ways, it's more convenient to use. | 19:11 |
| thoughtpolice | So there's a wide array of things it can do. | 19:11 |
| daveshah | As mentioned all of the code for converting the parsed SVAs to state machines for formal verification itself is written by Clifford and open source here: https://github.com/YosysHQ/yosys/blob/master/frontends/verific/verificsva.cc - once an open source SystemVerilog parser exists, it could be reused | 19:12 |
| tpb | Title: yosys/verificsva.cc at master · YosysHQ/yosys · GitHub (at github.com) | 19:12 |
| daveshah | But writing a good parser is a big challenge. That's why many big companies, including Xilinx and Lattice, use Verific in their synthesis tools | 19:13 |
| formalnewb | gotcha | 19:30 |
| formalnewb | thanks for the help | 19:30 |
| formalnewb | i guess i just truly did not understand what each tool was doing | 19:31 |
| formalnewb | sorry i was away for bit | 19:31 |
| daveshah | No worries! ZipCPU has some good articles about the open source tools on his blog http://zipcpu.com/ btw | 19:31 |
| tpb | Title: The ZipCPU by Gisselquist Technology (at zipcpu.com) | 19:31 |
| formalnewb | ill check out more of those articles | 19:32 |
| formalnewb | so in doing formal at home - without having verific or onespin at my disposal - for hobby projects i should stick to assertions that are defined in the verilog spec | 19:32 |
| formalnewb | not the system verilog spec | 19:32 |
| formalnewb | that way i can do formal with yosys | 19:32 |
| formalnewb | or rather, language features for assertions that are defined in verilog spec | 19:34 |
| daveshah | Yes, that's right - anything without `property` or `sequence` should be fine | 19:34 |
| daveshah | Yosys defines a few of its own extensions, like `$anyconst` and `$anyseq` for arbitrary constants and sequences (i.e. equivalent to SystemVerilog `rand`) | 19:34 |
| daveshah | I would be very interested to hear feedback on how Yosys/SymbiYosys compares to a commercial formal tool | 19:35 |
| formalnewb | is there a standard intermediate language that verific puts out that yosys takes in to understand? how does yosys know how to interpret the parsed SV that veriic puts out? | 19:36 |
| formalnewb | @daveshah if i get more time to play with yosys i can do a little comparison, at my work we have both JasperGold and OneSpin | 19:36 |
| daveshah | I believe it's all passed using C++ data structures between Yosys and the Verific library - see https://github.com/YosysHQ/yosys/blob/master/frontends/verific/verific.cc | 19:37 |
| tpb | Title: yosys/verific.cc at master · YosysHQ/yosys · GitHub (at github.com) | 19:37 |
| thoughtpolice | formalnewb: Verific is literally a C++ library you use, it comes with an API. | 19:37 |
| thoughtpolice | You need the library version for it to actually support all those features. There's a demo version that can just parse, but it's not sufficient. | 19:37 |
| thoughtpolice | (And it's not in API form, it's just an executable you can run to ensure Verific can handle your design, but that's it basically) | 19:38 |
| formalnewb | ah so the parsed SV that comes back is really all proprietary to verific | 19:38 |
| formalnewb | since they defined their data structures | 19:38 |
| daveshah | yes, that's right | 19:39 |
| formalnewb | so if one were to write their own systemverilog parser they need to basically understand what structures are needed to convert SV into netlists (or other low level description) of hardware and then implement those structures in an API | 19:40 |
| formalnewb | but that includes understanding how stuff like how different blocks correspond to different hardware logic like shift registers, etc | 19:41 |
| formalnewb | different SV blocks, that is | 19:41 |
| daveshah | I suspect most of that could be reused from the Verilog elaboration. It would mostly be a case of dealing with all the new constructs (`struct` etc). SystemVerilog has a downside compared to Verilog, in that the synthesisable subset of SystemVerilog is not officially defined | 19:42 |
| formalnewb | or at very minimum something that takes SV and turns it into its corresponding verilog implementation, then other verilog parsers could handle it | 19:42 |
| daveshah | Yes | 19:42 |
| formalnewb | i dont feel like i understand what verific is really doing if its just parsing SV and passing it along as proprietary data structures, how does that get closer to the true low level gate design? | 19:45 |
| daveshah | The output of Verific is lower level than just an abstract syntax tree, but higher level than a gate level design. So an `add` operation would create an instance of `OPER_ADDER` | 19:50 |
| formalnewb | huh, i see, so in order to write a parser you'd need to understand how all the different ways one could write the same logic to parser into the same structures? | 19:52 |
| * sorear idly wonders how the problem compares to the VHDL problem | 19:53 | |
| philtor | what's the VHDL problem? | 19:54 |
| sorear | yosys also currently lacks a VHDL parser | 19:54 |
| philtor | So, as I understand it, Verific sells parsers to companies making EDA tools. | 19:55 |
| philtor | yosys has a VHDL->Verilog converter, but haven't tried it out to know how well it works/doesn't work | 19:55 |
| philtor | It would definitely be nice to have an open source VHDL frontend. | 19:57 |
| philtor | Right now there's GHDL which is an open source VHDL simulator | 19:57 |
| philtor | But getting it to output something that yosys could use would be quite a task | 19:57 |
| philtor | It can now apparently output LLVM-IR, but that's lacking a lot of info that a synth tool would need | 19:58 |
| philtor | GHDL has been around a long time now and is still actively developed | 19:59 |
| philtor | Written in Ada, so not a lot of developers would be available, you'd think. | 19:59 |
| philtor | (not a knock on Ada, it actually has a lot of nice features) | 20:00 |
| formalnewb | are there any efforts for creating an open source SVA parser? | 20:04 |
| philtor | So apparently one can parse VHDL with Verific and feed that output to yosys. Does that mean there's a documented interface for this path into yosys? | 20:04 |
| philtor | (or one could apparently also parse SV with Verific and feed that to yosys) | 20:05 |
| formalnewb | philtor thats what i've been trying to understand that daveshah and thoughtpolice have been helping explain to me | 20:06 |
| formalnewb | SV parsed with verific then passed to yosys | 20:06 |
| formalnewb | the problem is i dont have verific as its expensive | 20:07 |
| formalnewb | pretty much not for hobbyists | 20:07 |
| philtor | yep. | 20:08 |
| philtor | Oh, I see above... "it's all passed using C++ data structures between Yosys and the Verific library - see https://github.com/YosysHQ/yosys/blob/master/frontends/verific/verific.cc: | 20:08 |
| philtor | " | 20:08 |
| philtor | VerificImporter | 20:09 |
| awygle | Regarding an open source SV parser, I find https://github.com/MikePopoloski/slang to be a very interesting effort | 20:14 |
| tpb | Title: GitHub - MikePopoloski/slang: SystemVerilog compiler and language services (at github.com) | 20:14 |
| awygle | The author doesn't seem to be active in any of the usual spaces, but is _very_ actively developing the project | 20:16 |
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| formalnewb | wow so it looks like its already in the works | 20:28 |
| awygle | Well I have no idea if the author of that project has any idea Yosys exists (I've never spoken with them) | 20:33 |
| awygle | I share it around occasionally just in case someone wants to do the work of integrating the two | 20:33 |
| daveshah | It looks interesting. I don't know how much you would need "in the middle" to get it working with Yosys - things like actually converting structs to packed signals, etc | 20:34 |
| awygle | Right, haven't looked in depth to see how far from RTLIL or the Yosys ast backend it is. | 20:36 |
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| formalnewb | zipcpu | 21:42 |
| formalnewb | you make the blog with the dope tutorials | 21:42 |
| formalnewb | i just started reading them | 21:42 |
| ZipCPU|Laptop | Welcome to the channel, fomalnewb, I've been out all day, and I'm just starting to catch up to the conversation. | 21:42 |
| formalnewb | yeah i asked a bunch of noobie questions and learned something haha | 21:42 |
| formalnewb | from the sound of it i've been doing formal the easy-peasy way with SystemVerilog | 21:43 |
| formalnewb | since it has nice hold-your-hand structures like sequences and implications | 21:43 |
| ZipCPU|Laptop | I've only been doing formal via yosys. | 21:43 |
| ZipCPU|Laptop | I've never tried any commercial tools, although I did just get started with Verific. | 21:43 |
| formalnewb | i'm sad that the only thing missing from bringing formal with SV to 100% free and open source is a FOSS SV parser | 21:44 |
| formalnewb | but thats life | 21:44 |
| ZipCPU|Laptop | Heh ... | 21:45 |
| ZipCPU|Laptop | there are easy conversions for most of what you've learned in SVA to OSS formal. | 21:45 |
| ZipCPU|Laptop | Sequences, though, will take a bit more work. | 21:45 |
| awygle | formalnewb: so write one! :P | 21:45 |
| * ZipCPU|Laptop is tempted to fix the parser | 21:45 | |
| formalnewb | haha i wish i knew enough to even begin to write one | 21:46 |
| ZipCPU|Laptop | sorry, to "complete" the parser would be clearer | 21:46 |
| * awygle stands behind ZipCPU|Laptop chanting "do it, do it, do it" | 21:46 | |
| ZipCPU|Laptop | Parser's aren't really all that hard, and most of the work is already done in the System Verilog specification | 21:46 |
| formalnewb | i wouldnt even know what kind of structures to implement to pass to yosys | 21:47 |
| ZipCPU|Laptop | For example, assert property(A |-> B) is easily converted to an always @(*) if (A) assert(B); | 21:47 |
| formalnewb | like what structures does verific output? | 21:47 |
| ZipCPU|Laptop | Just return that structure on a conversion ;) | 21:47 |
| formalnewb | that makes sense | 21:47 |
| formalnewb | does verilog support ##N > | 21:48 |
| formalnewb | ?* | 21:48 |
| formalnewb | like the cycle indicator | 21:48 |
| ZipCPU|Laptop | Or how about, assert property( @(posedge i_clk) A |=> B); That one converts nicely to always @(posedge i_clk) if ((f_past_valid)&&($past(A))) assert(B); | 21:48 |
| ZipCPU|Laptop | ##N is ... a little more difficult. | 21:48 |
| ZipCPU|Laptop | It's also more confusing. | 21:48 |
| ZipCPU|Laptop | You can read my comments and clifford's response in one of his recent tweats: https://twitter.com/oe1cxw/status/973930312991420417 | 21:49 |
| awygle | you should be able to fake it with e.g. a counter, surely? | 21:49 |
| ZipCPU|Laptop | awygle: Absolutely! | 21:49 |
| formalnewb | i guess i dont really know enough about assertions as they relate to actual implementation | 21:49 |
| ZipCPU|Laptop | But ... the translation is a bit more difficult I would think. (I've never done it) | 21:49 |
| formalnewb | like when i think about properties i just think of something that is separate from the hdl | 21:49 |
| formalnewb | i dont really think of it in terms of always blocks | 21:50 |
| daveshah | The basic idea is to generate a FSM based on the sequences and property | 21:50 |
| ZipCPU|Laptop | http://zipcpu.com/blog/2017/10/19/formal-intro.html | 21:50 |
| tpb | Title: My first experience with Formal Methods (at zipcpu.com) | 21:50 |
| daveshah | This is obviously easier for some sequences than others | 21:50 |
| ZipCPU|Laptop | The other thing is ... while the ##N property specifications are nice, you can actually do more in HDL | 21:51 |
| formalnewb | what do you mean "do more" | 21:51 |
| ZipCPU|Laptop | Hence, I've found the full SVA properties ... insufficient for proving the WB bus | 21:51 |
| ZipCPU|Laptop | http://zipcpu.com/zipcpu/2017/11/07/wb-formal.html | 21:52 |
| tpb | Title: Building Formal Assumptions to Describe Wishbone Behaviour (at zipcpu.com) | 21:52 |
| ZipCPU|Laptop | Sure, I can do some things ... I just can't match up requests with acknowledgements. | 21:52 |
| ZipCPU|Laptop | (One acknowledgment per request, no more, no less) | 21:52 |
| formalnewb | hmm | 21:52 |
| formalnewb | once i finish up my basic UART i will take a stab at installing yosys and get on with assertions | 21:52 |
| ZipCPU|Laptop | Go for it! | 21:53 |
| formalnewb | i shouldnt whine about not having FOSS tools that accept SV when formal itself is still new | 21:53 |
| formalnewb | i spend all my time doing work stuff that when i get home i dont want to bother working on hdl haha | 21:53 |
| ZipCPU|Laptop | Although I might warn you ... the UART is more complex to prove than a lot of other things. It's easy to build, harder to prove. | 21:53 |
| formalnewb | but simple things will be easy to prove for it | 21:53 |
| formalnewb | i just need a starting point | 21:54 |
| ZipCPU|Laptop | I hope to present the proof of a cache soon. That's one article I haven't written yet. | 21:54 |
| ZipCPU|Laptop | Starting point? Search zipcpu.com for the word formal. The intro article is fairly good. | 21:54 |
| formalnewb | oh i mean a starting point for a module to use with yosys | 21:55 |
| formalnewb | ive read your intro article | 21:55 |
| ZipCPU|Laptop | There's also an article on formal properties of a wb bus, a simple prefetch (using that bus), and more recently an exercise in using induction. | 21:55 |
| formalnewb | its a good one | 21:55 |
| formalnewb | the fifo is also a good starting point, which i saw you use | 21:55 |
| ZipCPU|Laptop | Thanks! | 21:55 |
| formalnewb | but i already starting working on my uart :p | 21:55 |
| ZipCPU|Laptop | Yeah, and I discovered my "working" FIFO ... wasn't. | 21:55 |
| formalnewb | im trying to build up a library of common modules to use for future hobby projects | 21:56 |
| * ZipCPU|Laptop pulls his tail between his legs, and hangs his head lower. | 21:56 | |
| ZipCPU|Laptop | formalnewb: You and me both. | 21:56 |
| formalnewb | unfortunately i cant use anything i write at work | 21:56 |
| ZipCPU|Laptop | All of mine are on Github, though: https://github.com/ZipCPU | 21:56 |
| tpb | Title: ZipCPU (Dan Gisselquist) · GitHub (at github.com) | 21:56 |
| formalnewb | so i often write it at work, then come home and rewrite it in my own style | 21:56 |
| formalnewb | this is a good collection | 21:57 |
| formalnewb | im thinking i'll just write a lot of the basic modules: uart, i2c, spi, debouncer, etc and try to testbench and formally prove some stuff about each one | 21:58 |
| formalnewb | just to give me a good background of verilog/system verilog, formal, and testbenching | 21:59 |
| formalnewb | i'm still fairly new to the whole fpga scene | 21:59 |
| awygle | well welcome aboard :) | 22:05 |
| ZipCPU|Laptop | Yes, definitely, welcome aboard! | 22:06 |
| formalnewb | thanks! it'll be a fun journey | 22:15 |
| formalnewb | so does everyone here do formal as a profession? | 22:15 |
| formalnewb | thats how i got into it | 22:16 |
| formalnewb | i didnt even know formal methods were a thing that existed until the project leader for my work asked me to learn onespin | 22:16 |
| ZipCPU|Laptop | Actually, No. I'm doing HDL as a profession. Formal is ... just a good way to better HDL. | 22:16 |
| ZipCPU|Laptop | I even met with the onespin team earlier this month. | 22:17 |
| ZipCPU|Laptop | Fun folks, I think highly of them no that I've met with some of them | 22:17 |
| formalnewb | one of them came to give a one-day bootcamp on the tool, he was very nice | 22:17 |
| ZipCPU|Laptop | I think they were a bit surprised to learn that Clifford had been using yosys to formally verify RISC-V designs. | 22:18 |
| formalnewb | its quite and undertaking | 22:20 |
| ZipCPU|Laptop | :) | 22:20 |
| ZipCPU|Laptop | Well ... I'm hoping to do more/better with the ZipCPU ... just haven't had the time (yet). | 22:25 |
| formalnewb | always the problem isn't it :p i feel like i have a trillion hobbies and no time to do any of them | 22:28 |
| formalnewb | its always scratching one thing off my to do list and then writing two more down :p | 22:28 |
| ZipCPU|Laptop | ... and I struggle to even get to the point of scratching one thing off ... | 22:30 |
| formalnewb | hahaha its a slow churn for me as well luckily i got out of grad school last year and working full time is exponentially more free time than grad school | 22:33 |
| ZipCPU|Laptop | Grad school grad w/ no family ... can probably contribute the most. :P | 22:38 |
| formalnewb | haha good luck, do it for all of us! | 23:07 |
| formalnewb | question: since verific seems like the only system verilog parser, does that mean tools like modelsim which are free to download use verific? | 23:08 |
| formalnewb | modelsim does support SV | 23:08 |
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| ZipCPU|Laptop | formalnewb: Yes. Verific is a complete parser that is used by *many* Verilog based projects. | 23:51 |
| ZipCPU|Laptop | I've seen Verific errors from Vivado and ISE as examples. | 23:51 |
| ZipCPU|Laptop | I think Verific is even within Quartus, but I haven't seen evidence of that one way or another. | 23:51 |
| formalnewb | so is it at all possible to get one of the free tools that uses verific to output a lower level abstraction of the system verilog that yosys can take it? | 23:54 |
| formalnewb | take in* | 23:54 |
| formalnewb | like compile/parse with modelsim then export to yosys | 23:55 |
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