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acomodi | kem_: Hi, I have created a PR with an implementation of equivalent tiles https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/559 | 13:37 |
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tpb | Title: WIP [DNM]: Equivalent Tiles placement by acomodi · Pull Request #559 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 13:37 |
acomodi | kem_: It currently fails on CI as there the PR also moves the top level pb_types-only tags to the tiles tags (which are not present in the current test architectures) | 13:38 |
acomodi | kem_: can you have a look at it and give me feedback when you have some time, please? | 13:42 |
acomodi | kem_ : I have tested it within the symbiflow environment and it correctly places clustered blocks in equivalent tiles and VTR produces valid outputs that do work on HW | 13:43 |
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litghost | kem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/563 | 18:54 |
tpb | Title: Placement delta delay block choice seems limited · Issue #563 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:54 |
litghost | kem_: Should https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/place/place.cpp#L2230 generate an error on non-finite delay values? | 21:44 |
tpb | Title: vtr-verilog-to-routing/place.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 21:44 |
litghost | kem_: It tests for < 0, but I have a case where it generated "inf" | 21:44 |
litghost | kem_: And it's for blocks that definitely have connectivity | 21:44 |
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