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| litghost | kem_: Is there a way to describe in a pb_type a 1 input 1 output mux that fans out to >1 blackboxes? | 22:54 |
|---|---|---|
| litghost | kem_: I think all 3 interconnect descriptions reduce to N muxes to each black box, rather than 1 mux which then fans out | 22:55 |
| mithro | litghost: Take a look at "option 2" -> https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/284 | 23:09 |
| tpb | Title: Best way to express "routing BELs" in vpr · Issue #284 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 23:09 |
| litghost | mithro: You have the fanout backwards | 23:11 |
| litghost | mithro: So that won't work | 23:11 |
| mithro | https://www.irccloud.com/pastebin/sUAdZMZx/ | 23:14 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 23:14 |
| litghost | Ya, you didn't read the question. This about fanout AFTER the mux, e.g the mux output signal goes to multiple black boxes | 23:16 |
| litghost | That example isn't fanout at all | 23:16 |
| mithro | litghost: That has a MUX on a single input which it then fans out the value to multiple outputs? | 23:17 |
| litghost | mithro: But there is only a fan out of 1 | 23:17 |
| litghost | mithro: I'm saying say the mux chooses A5Q, then connect A5Q to 5 black boxes | 23:18 |
| litghost | mithro: E.g. fanout | 23:18 |
| mithro | litghost: That is exactly what the xml I pasted above does.... | 23:19 |
| litghost | mithro: Each connection is modelled as a mux, there is only 1 mux | 23:20 |
| mithro | litghost: My example only has a single mux | 23:20 |
| litghost | mithro: A <direct> is actually a configurable signal. I'm saying that the fanout is a net, e.g. a short | 23:20 |
| litghost | mithro: direct's do not model fanout, they model switches | 23:20 |
| litghost | mithro: VPR can choose to "connect" only the direct's that it wants too | 23:21 |
| mithro | That doesn't seem right to me | 23:22 |
| litghost | https://github.com/SymbiFlow/vtr-verilog-to-routing/blob/master%2Bwip/vpr/src/pack/pb_type_graph.cpp#L379 | 23:25 |
| tpb | Title: vtr-verilog-to-routing/pb_type_graph.cpp at master+wip · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 23:25 |
| litghost | DIRECT_INTERC and MUX_INTERC literally use the same code to wire themselves | 23:26 |
| litghost | I guess that might be pins only :/ | 23:27 |
| litghost | mithro: Ya, I just ran a test | 23:33 |
| litghost | mithro: direct's are consider configurable by VPR | 23:33 |
| litghost | mithro: It's possible that a "short" type is required to model what I want to represent, we'll see what kem_ says | 23:34 |
| litghost | mithro: Basically want we want to <direct input="a" output="b"> <short input="b" output="c"> <short input="b" output="d">, if a signal appears on b, it will be sent to "c" and "d" | 23:36 |
| litghost | mithro: Right now VPR will happly pack a "d" == OPEN with a "c" == "net" | 23:36 |
| mithro | Seems like it would need to be fixed at https://github.com/SymbiFlow/vtr-verilog-to-routing/blob/master%2Bwip/vpr/src/pack/cluster_router.cpp#L1179-L1212 ? | 23:38 |
| tpb | Title: vtr-verilog-to-routing/cluster_router.cpp at master+wip · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 23:38 |
| mithro | litghost: Maybe turn on PRINT_INTRA_LB_ROUTE define? | 23:39 |
| litghost | mithro: Is that an echo file, or #define only? | 23:39 |
| mithro | #define only it seems | 23:39 |
| mithro | https://github.com/SymbiFlow/vtr-verilog-to-routing/blob/master%2Bwip/vpr/src/pack/cluster_router.cpp#L1243 | 23:39 |
| tpb | Title: vtr-verilog-to-routing/cluster_router.cpp at master+wip · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 23:40 |
| mithro | https://github.com/SymbiFlow/vtr-verilog-to-routing/blob/master%2Bwip/vpr/src/pack/cluster_router.cpp#L38 | 23:40 |
| tpb | Title: vtr-verilog-to-routing/cluster_router.cpp at master+wip · SymbiFlow/vtr-verilog-to-routing · GitHub (at github.com) | 23:40 |
| litghost | mithro: That is only printed on routing failure, I'm having a case where a routing conflict was not detected | 23:41 |
| litghost | mithro: To be honest, I wasn't sure if VPR treated an "open" black box port as a don't care, but I don't think that is what is happening | 23:41 |
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