| *** tpb has joined #vtr-dev | 00:00 | |
| litghost | kem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/524 | 01:20 |
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| tpb | Title: Wire length metric incorrectly terminates routing iterations · Issue #524 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 01:20 |
| litghost | kem_: I've seen at least one case where VPR generated an "antenna" net, e.g. a route that enters a channel but never leaves it | 16:03 |
| litghost | kem_: I consider this behavior suprising, possible bug? | 16:03 |
| litghost | kem_: This is using switches with mux's and short's, so adding the "antenna" net shouldn't modify timing because the isolation of the mux switch | 16:04 |
| kem_ | litghost: You mean effectively a 'stub' branch of the route tree which doesn't connect to any sink? | 16:06 |
| litghost | kem_: Yes | 16:07 |
| kem_ | litghost: If the driver of that wire is configurable (i.e. a mux) then yes that would be unexpected | 16:07 |
| litghost | kem_: Okay, later today I'll write up a bug with the arch and graph | 16:08 |
| mithro | kem_: Would you be free tomorrow morning to look at landing some of the formatting changes for the EXTERNAL libs? | 16:27 |
| litghost | kem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/526 | 18:35 |
| tpb | Title: Router generating "stub" or "antenna" nets · Issue #526 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:35 |
| litghost | kem_: I might be missing something, but I'm relatively confident this is a real issue | 18:36 |
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