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| litghost | kem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/479 | 00:03 |
|---|---|---|
| tpb | Title: High fanout routing logic causes routing failure · Issue #479 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 00:03 |
| litghost | Some of the routing checks have to be disabled, hence https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/478 | 00:03 |
| tpb | Title: WIP: Replicate fan out issue by litghost · Pull Request #478 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 00:04 |
| litghost | https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/478 also contains https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/473 because the arch and rrgraph have metdata | 00:04 |
| tpb | Title: WIP: Replicate fan out issue by litghost · Pull Request #478 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 00:04 |
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| litghost | kem_: Have you had a chance to look at https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/473 ? | 17:27 |
| tpb | Title: Add metadata support to architecture and rr_graph XML. by litghost · Pull Request #473 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 17:27 |
| kem_ | litghost: I had a quick browse through it, but haven't had time to write up a review in detail... hopefully in the next couple of days | 17:53 |
| litghost | kem_: Thanks! | 17:53 |
| litghost | kem_: We found https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/485 when updating as well, unclear what changed. | 17:53 |
| tpb | Title: Placer fails with final cost check error · Issue #485 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 17:53 |
| litghost | kem_: I'm going to bisect to see if I can find when the regression was introduced | 17:53 |
| kem_ | litghost: Yeah I've seen that a couple of times as well. It relates to the difference between calculating incremental cost changes vs calculating costs from scratch, which can result in differing floating point round-off | 17:56 |
| kem_ | litghost: Bisecting it would be good | 17:56 |
| kem_ | litghost: Although it may not be a particular change which is the root cause... it could just be a particular change causes a different optimization path to be followed which results in the round-off differences exceeding the current thershold | 17:57 |
| litghost | kem_: Is https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/483 something VPR could accept? It's unclear if this is a bug in VPR or a requirement on tiles | 18:06 |
| tpb | Title: Allow tiles with only sources or sinks. by litghost · Pull Request #483 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:06 |
| kem_ | litghost: We've usually modelled I/Os as being bi-directional (since most FPGA pins can be configured either way). | 18:10 |
| kem_ | litghost: I don't see any problem allowing dedicated inputs/outputs with a single source/sink, so long as any code depending there being both is updated to work. | 18:11 |
| litghost | kem_: I think https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/483 is the only change, as the testarch in https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/485 does route with https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/483 | 18:12 |
| tpb | Title: Allow placement of tiles with only sources or sinks. by litghost · Pull Request #483 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:12 |
| litghost | kem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/485#issuecomment-470213620 | 18:17 |
| litghost | I've tracked down the regression to the "cluster_seed_type". It does mean I have a workaround, but does that help point you to a fix? | 18:17 |
| tpb | Title: Placer fails with final cost check error · Issue #485 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:17 |
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