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| digshadow | elms, mithro: was able to get a up5k design fully through the perf tool pipeline | 00:02 |
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| digshadow | (using vpr) | 00:02 |
| mithro | digshadow: Awesome! | 00:03 |
| digshadow | also I'm noticing that the radiant strategy option seems to be ignored, not sure if thats worth looking into | 00:05 |
| digshadow | at least for simple designs. Maybe once I throw an SoC in it will do something more interesting | 00:05 |
| mithro | digshadow: Sounds pretty normal :-P | 00:05 |
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| mithro | kem_: Random question for you https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/375 | 04:12 |
| tpb | Title: Why does VPR prevent clock driving both data and clock pins? · Issue #375 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 04:12 |
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| mithro | kem_: Morning! Hope those papers are going well | 15:47 |
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