| *** tpb has joined #vtr-dev | 00:00 | |
| daveshah | mithro: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/351#issuecomment-396056011 | 15:09 |
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| tpb | Title: How to model "mutually exclusive" fan out in a rr_graph.xml · Issue #351 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 15:09 |
| daveshah | if it's any consolation, this wasted most of Clifford and my days... | 15:09 |
| mithro | daveshah: interesting | 20:34 |
| daveshah | mithro: arachne-pnr actually marks these as bidir in its routing graph, but fortunately ignores that due to an omission in the router! | 20:36 |
| daveshah | Anyway, it looks like everything in the ice40 is unidir so that issue can be closed, although I may poke about a bit to make absolutely sure | 20:37 |
| mithro | daveshah: well that makes things a lot easier | 20:41 |
| daveshah | yeah | 20:41 |
| mithro | What made you look at it again? | 20:41 |
| daveshah | Such discussions are beyond my pay grade :P | 20:41 |
| mithro | Well it seems like I have logic equivalence working for VtR on the blif and Verilog output | 20:48 |
| mithro | So the problem must be in my HLC output or the HLC conversion | 20:49 |
| daveshah | mithro: my feeling is its in the LUT rotation | 20:50 |
| daveshah | or possibly auto generated pass through LUTs | 20:50 |
| mithro | Yeah | 20:50 |
| daveshah | But good to know its not a core vpr issue | 20:50 |
| mithro | My feeling too | 20:50 |
| daveshah | For the former, feels like a case of pencil and paper debugging would be best | 20:50 |
| mithro | But i'm struggling with not really knowing how the LUT init bits work | 20:51 |
| daveshah | It is simply a 16 bit ROM | 20:53 |
| daveshah | Concatenate the inputs together, I0 as LSB, and use that as an index | 20:53 |
| mithro | I also know pretty much were things are broken | 20:53 |
| mithro | The Sim target shows exactly which signals are involved | 20:54 |
| daveshah | mithro: this might help more? https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v#L121 | 20:55 |
| tpb | Title: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at github.com) | 20:55 |
| daveshah | Yeah, should be possible to find the same lut in the official netlist and compare | 20:55 |
| mithro | daveshah: it would be really nice if the bitstream to Verilog generated LUTs instead of the weird try states it does | 20:57 |
| daveshah | mithro: for now, have a look at the icestorm_explain output for LUT values | 20:58 |
| daveshah | I think icetime might produce a Verilog netlist with LUTs too, but I haven't tried | 20:58 |
| mithro | Be back in 20 | 20:58 |
| daveshah | icebox_vlog does what it does to produce a functional netlist that is platform independent and works anywhere without being too large | 20:59 |
| mithro | So now it's "This section lists the routing configuration bits in the tile. All routing resources are directional tristate buffers that are in tristate mode in the all-zeros configuration. " | 21:23 |
| daveshah | mithro: Yeap | 21:25 |
| daveshah | Probably worth eliminating the bidirectional stuff from HLC too | 21:25 |
| mithro | daveshah: Does this look right? | 21:28 |
| mithro | https://paste.ubuntu.com/p/9CCfhNFDK4/ | 21:28 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 21:28 |
| daveshah | Also let me know if you see references to bidirectional switches anywhere else in ice40/icestorm stuff so I can remove them | 21:28 |
| mithro | daveshah: Specifically the in_0 / in_3 / in_1 luts? | 21:28 |
| daveshah | mithro: they look the wrong way round in the normal order | 21:29 |
| daveshah | If that is MSB first | 21:29 |
| daveshah | I think it's LSB first though, then it's fine | 21:30 |
| mithro | daveshah: It's the format HLC uses internally.... | 21:30 |
| daveshah | That's what icebox_explain uses | 21:30 |
| daveshah | No idea what HLC uses | 21:30 |
| mithro | The stuff below is what icebox explain uses | 21:30 |
| daveshah | But the Verilog models are MSB first, so be careful | 21:30 |
| daveshah | I think HLC and icebox_explain are the same | 21:31 |
| daveshah | So it's fine | 21:31 |
| daveshah | But IMO putting 16'b before somethint makes it look like it should be MSB first, which is confusing | 21:31 |
| mithro | daveshah: But then I'm outputing them in the wrong order I think.... | 21:32 |
| daveshah | I don't know what VPR uses internally | 21:33 |
| daveshah | I would expect nothing to work correctly if they were the wrong way round | 21:33 |
| daveshah | I'm fairly certain your ordering is correct, but a bit confusing | 21:33 |
| mithro | daveshah: Yeah - I would expect all my lut tests to fail | 21:34 |
| daveshah | I would probably remove the 16'b prefix in HLC. Then it is clear it is in icebox_explain, LSB first order. | 21:35 |
| mithro | ['out', '=', "16'b0010000000000000"] 0010000000000000 | 21:37 |
| mithro | That looks wrong for a route-through-in1 ? | 21:37 |
| daveshah | Yes, that's not right at all | 21:37 |
| mithro | Yet it seems to pass equivalence checking? | 21:38 |
| daveshah | Sorry, its fine actually | 21:38 |
| daveshah | All the other inputs are 0 | 21:39 |
| daveshah | That truth table implies output is high when the inputs are equal to 2 (0b0010) | 21:39 |
| mithro | daveshah: ['out', '=', 'in_1'] 0011001100110011 | 21:40 |
| daveshah | Equally valid solutions | 21:40 |
| mithro | Oh? | 21:40 |
| daveshah | The former only works when all other inputs are zero, but that is the case in hardware if they are not driven | 21:40 |
| mithro | daveshah: The first one? | 21:41 |
| daveshah | Yeah, but both should work | 21:41 |
| daveshah | I know 010000... works as a pass through for in0 | 21:42 |
| mithro | https://www.irccloud.com/pastebin/q99MQFcG/ | 21:42 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 21:42 |
| daveshah | That should produce something like 0000 0000 1000 0000 | 21:44 |
| daveshah | If inputs are not rotated | 21:44 |
| daveshah | If they are, there should still only be one 1 but in a different position | 21:44 |
| daveshah | Anyway, bed for me now | 21:46 |
| mithro | daveshah: https://paste.ubuntu.com/p/yrvTt6C5bZ/ | 21:49 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 21:49 |
| mithro | daveshah: Your right about the icetime output being easier to look at | 21:52 |
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