| *** tpb has joined #vtr-dev | 00:00 | |
| mithro | daveshah: Morning | 15:00 |
|---|---|---|
| daveshah | mithro: morning | 15:00 |
| mithro | daveshah: How's things over in Austria? | 15:01 |
| daveshah | mithro: Things aren't going too badly | 15:01 |
| daveshah | Did you get a chance to work on the tile config? | 15:02 |
| mithro | daveshah: I added arbitrary metadata to pb_types -- still working on getting them in the output in a nice way | 15:07 |
| daveshah | mithro: nice | 15:08 |
| mithro | daveshah: I don't think I understand how the bits in the bitstream work for the set/reset sync/Async stuff? | 16:33 |
| daveshah | mithro: let me look, haven't looked at those for a while | 16:33 |
| mithro | Basically how they map to the SB_FF primitives... | 16:34 |
| daveshah | the relevant bits are the LC_i bits IIRC | 16:34 |
| daveshah | see some info here: http://www.clifford.at/icestorm/logic_tile.html | 16:34 |
| tpb | Title: Project IceStorm LOGIC Tile Documentation (at www.clifford.at) | 16:34 |
| mithro | LC_i[18] is the Set_NoReset bit. When this bit is set then the set/reset signal will set, not reset the flip-flop. | 16:35 |
| mithro | LC_i[19] is the AsyncSetReset bit. When this bit is set then the set/reset signal is asynchronous to the clock. | 16:35 |
| daveshah | c.f. also https://github.com/cseed/arachne-pnr/blob/master/src/pack.cc#L155 | 16:35 |
| tpb | Title: arachne-pnr/pack.cc at master · cseed/arachne-pnr · GitHub (at github.com) | 16:35 |
| daveshah | and https://github.com/cseed/arachne-pnr/blob/master/src/place.cc#L1604 | 16:35 |
| tpb | Title: arachne-pnr/place.cc at master · cseed/arachne-pnr · GitHub (at github.com) | 16:35 |
| mithro | daveshah: thanks! That arachne code looks exactly what I was trying to understand. | 16:37 |
| daveshah | mithro: yep, implement the same behaviour in pack.cc and you should be golden | 16:38 |
| daveshah | probably worth looking at the carry stuff there too | 16:38 |
| mithro | daveshah: I'm not entirely happy with it -- but I have the enable_ff / disable_ff properties coming through now | 18:59 |
| daveshah | mithro: great | 19:00 |
| mithro | daveshah: This is what I have at the moment -> http://hopper.mithis.com/~tim/top.hlc | 19:06 |
| mithro | daveshah: This seems a bit weird... | 19:08 |
| mithro | https://www.irccloud.com/pastebin/cbVX8l3s/ | 19:08 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 19:08 |
| daveshah | mithro: yeah | 19:08 |
| daveshah | not sure what's going on | 19:09 |
| daveshah | check the blif.. | 19:09 |
| mithro | daveshah: .names counter[9] counter[8] counter[7] $abc$1289$n57_1 $abc$1289$n56_1 1111 1 | 19:12 |
| daveshah | hmmm, almost looks as if the output is the wrong way round | 19:12 |
| daveshah | it is perhaps supposed to be a 4-input AND | 19:12 |
| daveshah | I think that's what the BLIF is (I hate interpreting BLIF gates) | 19:13 |
| mithro | Would that be a 4 input NAND? | 19:14 |
| daveshah | 16'b0000000000000001 is a 4-input NOR, surely? | 19:15 |
| daveshah | but I think the BLIF is a 4-input AND, aka 16'b1000000000000000 | 19:15 |
| daveshah | you might want to run a small test through first to check | 19:15 |
| mithro | daveshah: http://hopper.mithis.com/~tim/lut-top.hlc | 19:18 |
| mithro | daveshah: From https://github.com/mithro/symbiflow-arch-defs/blob/4mcmaster/tests/common/3-lut/lut.v | 19:19 |
| tpb | Title: symbiflow-arch-defs/lut.v at 4mcmaster · mithro/symbiflow-arch-defs · GitHub (at github.com) | 19:19 |
| mithro | daveshah: http://hopper.mithis.com/~tim/lut.eblif | 19:19 |
| daveshah | mithro: yeah I think the LUTs in the HLC are the wrong way round by the usual convention, that I think the Yosys verilog uses | 19:21 |
| mithro | What do you mean by "wrong way around" ? | 19:21 |
| daveshah | Bit 15 and 0 need the be swapped, etc | 19:22 |
| mithro | daveshah: Oh - the bit ordering... | 19:22 |
| daveshah | But I don't know what's parsing this, AFAIK the HLC parser in master requires an expression not an integer for LUT init | 19:22 |
| daveshah | I think jhol added that to his fork? | 19:22 |
| daveshah | Anyway, best thing to try is running an inverter through to HLC and then back through icebox_vlog | 19:23 |
| jhol | daveshah: correct | 19:23 |
| mithro | jhol: So - which way around does your hlc change expect the lut vector? | 19:23 |
| jhol | the right way ;) | 19:24 |
| mithro | jhol: I'm using your code to output the LUT value :-P | 19:24 |
| jhol | --- it seemed to be working correctly when I last checked it-- I exported a LUT to HLC to ASC, then converted it back to HLC and the expression was correct | 19:25 |
| mithro | jhol: jhol/hlc-work ? | 19:25 |
| jhol | yes | 19:26 |
| jhol | I guess the LSB should be I[0:3] = 4'b0000, and the MSB should be 4'b1111 | 19:26 |
| daveshah | yeah, that then matches https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/cells_sim.v#L121 | 19:26 |
| tpb | Title: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at github.com) | 19:26 |
| mithro | jhol/ daveshah: well "make check" works for iceinv :-P | 19:31 |
| daveshah | jhol: awesome | 19:31 |
| daveshah | *mithro: awesome | 19:31 |
| mithro | I assume that is what | 19:32 |
| mithro | SAT proof finished - no model found: SUCCESS! | 19:32 |
| mithro | means... (with a giant QED).... | 19:32 |
| daveshah | sounds good | 19:32 |
| daveshah | post the icebox_vlog | 19:32 |
| mithro | https://www.irccloud.com/pastebin/Y05RWUtF/ | 19:34 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 19:34 |
| daveshah | yep, looks good | 19:34 |
| mithro | daveshah / jhol: I pushed all my changes - want to give it a go? | 19:35 |
| daveshah | rebuilding vpr now | 19:37 |
| mithro | daveshah: You need 4mcmaster branches of vpr, symbiflow-arch-defs and icestorm | 19:39 |
| daveshah | no dice for me, looks like IO config is missing | 19:43 |
| daveshah | ERROR: Found posedge/negedge event on a signal that is not 1 bit wide at /home/david/symbiflow-arch-defs/tests/ice40/iceinv/build-ice40-top-routing-virt-HX1K/example_bitstream.v:53! | 19:44 |
| daveshah | mithro ^ | 19:44 |
| mithro | daveshah: hrm -- I wonder why it worked that first time... | 19:47 |
| daveshah | maybe I need to rebuild either VPR or the arch-defs, trying both | 19:47 |
| mithro | daveshah: I'm getting the same here.... | 19:47 |
| daveshah | mithro: are you outputting any IO tile config? | 19:48 |
| mithro | daveshah: Appears not - I must have manually added them ... | 19:51 |
| daveshah | mithro: makes sense then :P | 19:51 |
| mithro | daveshah: I should be though.... | 19:51 |
| daveshah | mithro: weird | 19:52 |
| mithro | daveshah: It appears I'm not dealing with the capacity="2" properly... | 19:52 |
| mithro | https://www.irccloud.com/pastebin/l3fSachL/ | 19:53 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 19:53 |
| mithro | daveshah: make check is working now | 23:02 |
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