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| mithro | digshadow: I think I need to output the name + tile for each *edge* rather than just the name for each node... | 00:08 |
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| benreynwar | mithro: Yeah, that's pretty painful. I checked a slow and simple implementation and it's much faster. I'll push a slow and simple solution, and at some point in the future if it becomes necessary for large devices I'll work out why the fast solution is so much slower. | 00:24 |
| mithro | benreynwar: Did it complete for you? | 00:25 |
| benreynwar | mithro: No, but I put some print statements in and could see it was going to take far longer than was sane. | 00:25 |
| mithro | benreynwar: Is that using the lookup edge<->node table thingy? | 00:26 |
| benreynwar | mithro: Nope. For the complicated version, I'm pretty sure that it's mostly that my algorithm sucks. | 00:27 |
| benreynwar | mithro: The simple version takes one or two minutes which should be fine if you don't have to run it often. | 00:27 |
| mithro | benreynwar: I wouldn't be so sure, look at https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/utils/lib/rr_graph/graph.py#L1898-L1923 | 00:28 |
| tpb | Title: symbiflow-arch-defs/graph.py at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 00:28 |
| mithro | You most certainly want to use https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/utils/lib/rr_graph/graph.py#L1874-L1896 | 00:28 |
| tpb | Title: symbiflow-arch-defs/graph.py at master · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 00:28 |
| mithro | benreynwar: Ahh -- looks like you already fixed that | 00:29 |
| benreynwar | mithro: Yep. | 00:30 |
| benreynwar | mithro: I just closed the pull request and open a new one with the simple solution (https://github.com/SymbiFlow/symbiflow-arch-defs/pull/133). The scaling is ugly (N^2) but it's nice and simple and works fast enough. | 00:47 |
| tpb | Title: utils: Add utility to check that all sources can route to all sinks. by benreynwar · Pull Request #133 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 00:47 |
| mithro | kem_: You wouldn't happen to be around -- Any idea how to get the edge id while looping over the output from route_ctx.trace_head? | 00:48 |
| mithro | prev_ptr->iswitch = device_ctx.rr_nodes[inode].edge_switch(iedge); | 00:54 |
| mithro | IE - Inverse of that... | 00:54 |
| mithro | digshadow: So -- it seems that edges don't have ids... | 01:04 |
| mithro | digshadow: http://vtr-verilog-to-routing.readthedocs.io/en/latest/vpr/file_formats.html#edges | 01:04 |
| tpb | Title: File Formats Verilog-to-Routing 8.0.0-dev documentation (at vtr-verilog-to-routing.readthedocs.io) | 01:05 |
| digshadow | mithro: make a key based on source + dest | 01:27 |
| mithro | digshadow: Yeah | 01:27 |
| mithro | benreynwar: does your new pull request work with the real rr_graph I posted? | 01:49 |
| benreynwar | mithro: In runs in a couple of minutes. It finds a bunch of unconnected (src, sink) pairs. Is that expected? | 01:50 |
| mithro | benreynwar: well - it atleast matches what vpr is complaining about | 01:50 |
| benreynwar | mithro: I forgot to add the test back in. It should do that. | 01:56 |
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| mithro | https://www.irccloud.com/pastebin/wd9bsP3x/ | 08:11 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 08:11 |
| mithro | Something funky is going on.... | 08:11 |
| kem_ | mithro: As I think you figured out, RR graph edges don't have unique Ids themselves. They are identified by the combination of source node Id and index within the source node edge array. | 13:29 |
| kem_ | mithro: I've thought about refactoring the RR graph so each edge has a unique Id (i.e. so it looks more like the AtomNetlist). However it would be a fair amount of code churn, so I've never got round to it. | 13:31 |
| mithro | kem_: Yeah | 17:07 |
| mithro | kem_: I've ended up just making it possible to have arbitrary metadata on both rr_nodes and rr_edges | 17:08 |
| mithro | kem_: Will rethink it a bit once I have something which works | 17:11 |
| mithro | daveshah: morning? | 17:14 |
| mithro | daveshah: I figured out why I was getting invalid bit patterns.... still working on a fix | 17:15 |
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| digshadow | mithro: hows it going? were you able to resolve the edge problem fully? | 18:02 |
| daveshah | mithro: morning | 18:05 |
| mithro | digshadow: Fighting with C++ currently | 18:16 |
| mithro | digshadow: I would say C++ is currently winning :-P | 18:16 |
| mithro | \o/ | 20:18 |
| mithro | digshadow / daveshah: No longer have any invalid routing nodes... | 20:19 |
| digshadow | mithro: !!!! | 21:17 |
| digshadow | are we popping champagne yet? | 21:17 |
| mithro | I still don't have the internals of the tiles yet... | 21:17 |
| digshadow | ? I thought daveshah did that already? | 21:17 |
| mithro | digshadow: jhol did a bunch of that - but I've broken it in the process of getting the routing working | 21:18 |
| digshadow | er gotcha | 21:19 |
| mithro | digshadow: Dammit - I'm now getting an issue because there seems to be routing in a RAM tile being used... | 23:10 |
| mithro | digshadow: Still trying to figure out how we have edges in a ram tile... | 23:24 |
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