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| mithro | digshadow: So in trying to get you an arch.xml which generates that rr_graph.xml example you had I think I ran into another bug | 01:07 |
|---|---|---|
| mithro | jhol: FYI -> https://github.com/SymbiFlow/symbiflow-arch-defs/pull/95 | 01:23 |
| tpb | Title: ice40: Getting the top-routing mode working by mithro · Pull Request #95 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 01:23 |
| digshadow | mithro: what did you find | 01:24 |
| mithro | digshadow: I got stuck at https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/332 before going of and doing other things | 01:25 |
| tpb | Title: No switch is specified for the ipin cblock · Issue #332 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 01:25 |
| digshadow | <fixed_layout height="2" name="JOHN" width="3"> | 01:26 |
| digshadow | I feel honored, a layout has been named after me! | 01:26 |
| digshadow | mithro: you don't have expected behavior | 01:27 |
| digshadow | I'm not actually clear from your description if this is expected or not | 01:28 |
| digshadow | you believe you specified the switch, but it dropped it? | 01:28 |
| digshadow | the bit of code you pointed to says something about multiple fanin, I don't think that will effect the tests I'm doing now | 01:30 |
| mithro | kem_: Have you seen http://www.rapidwright.io/ ? | 01:36 |
| tpb | Title: RapidWright (at www.rapidwright.io) | 01:36 |
| digshadow | looks like last rapidsmith update was in 2014 | 01:54 |
| digshadow | hosted on svn sourceforge I think, so not as easy to compare vs github | 01:54 |
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| mithro | digshadow: Yeah | 14:58 |
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| mithro | Morning kem_! Thanks for the bug fixes | 15:07 |
| mithro | kem_: Always awesome to wake up and see things having progressed | 15:07 |
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| jhol | kem_: I fixed those files you pointed out | 15:40 |
| kem_ | jhol: Great! Once CI finishes I should be able to merge it. | 15:41 |
| jhol | kem_: thanks! | 15:43 |
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| mithro | jhol: Morning! | 17:23 |
| mithro | jhol: How goes the PLB? | 17:26 |
| mithro | jhol: Did you see my pull request? | 17:27 |
| jhol | hi mithro: the HLC is coming along | 17:51 |
| jhol | I'm getting quite close to having the tiles and the internal tile routing being written out | 17:51 |
| jhol | then there's the LUT config and the and various other attributes to convert | 17:52 |
| jhol | the main issue is that I can't really do the conversion for things like the span-wire switches until the rr_graph is completed | 17:56 |
| jhol | are you refering to this PR?: https://github.com/SymbiFlow/symbiflow-arch-defs/pull/95 | 17:56 |
| tpb | Title: ice40: Getting the top-routing mode working by mithro · Pull Request #95 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 17:56 |
| mithro | jhol: Yes | 17:56 |
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| jhol | what's the reason for the unidirectional segment wires? | 17:57 |
| jhol | also, with your cascade test, did you see the LOUT pin routing through to the adjacent I2 properly? | 18:01 |
| mithro | jhol: bidir segments appear to be broken in some way -> https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/331 | 18:02 |
| tpb | Title: "found non-adjacent segments" in rr_graph when using bidirectional tracks · Issue #331 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:02 |
| jhol | ugh | 18:02 |
| jhol | mithro: have you guys though about how we're going to fudge the IO tiles? | 18:14 |
| mithro | jhol: Not really | 18:14 |
| jhol | I get the feeling that I'm going to need to spend some time on a pb_type for it, unless you have a really well thought out plan for how it can be fudged | 18:14 |
| jhol | at the moment our arch XML claims that it has 1-pad in the tile | 18:15 |
| jhol | just to give a bit more detail, this is the HLC format I'm replicating: https://paste2.org/HIy5LZaZ - this file contains a counter | 18:16 |
| jhol | here's what I have so far: https://paste2.org/By0cd4Pf | 18:16 |
| jhol | doesn't look like much, but it's been quite complex to get this far | 18:17 |
| jhol | the plan is to get the strings from the nodes from the XML names - the BLK_BB-xxx strings can be set up to match the inputs required by icebox_hlc2asc | 18:17 |
| jhol | the interal routing traversal is quite close, but there are one or two known issues to iron out | 18:21 |
| jhol | as I say, I can't do the '<->' statements for the span wires until the rr_graph is close to being usable | 18:21 |
| jhol | as for the io_tiles, I could hard-code some text into those, but we need to work how we would like the tile to terminate in the RR graph | 18:21 |
| mithro | jhol: BTW Did you see the verilog output code that inside vpr? | 18:21 |
| jhol | I know about it - didn't use it yet | 18:22 |
| mithro | jhol: There might be code you can steal from that for the LUT init stuff | 18:22 |
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| mithro | jhol: I know there is code in there for doing the LUT rotation | 18:22 |
| jhol | for that I was thinking of modifying hsc2asc to accept a bitmap for that field - but maybe the verilog way would be more elegant | 18:24 |
| mithro | jhol: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/base/netlist_writer.cpp | 18:25 |
| tpb | Title: vtr-verilog-to-routing/netlist_writer.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:25 |
| jhol | nice! - thanks | 18:25 |
| mithro | - We can write out the truth table as either a set of minterms (where the function is true), or a set of maxterms (where the function is false). We choose the representation which produces the fewest terms (and is smallest to represent in BLIF). | 18:26 |
| jhol | perfect! | 18:26 |
| mithro | jhol: I should have pointed you to that file earlier | 18:27 |
| mithro | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/base/netlist_writer.cpp#L1647-L1677 | 18:28 |
| tpb | Title: vtr-verilog-to-routing/netlist_writer.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:28 |
| mithro | //Returns a LogicVec representing the LUT mask of the given LUT atom | 18:28 |
| mithro | jhol: When you get a moment, can you send a WIP pull request so I can take a quick look and make sure you are heading in the right direction? | 18:31 |
| jhol | sure - I'm about to step out, but you can take a look at what I have | 18:33 |
| jhol | mithro: https://github.com/jhol/vtr-verilog-to-routing/commits/hlc | 18:35 |
| tpb | Title: Commits · jhol/vtr-verilog-to-routing · GitHub (at github.com) | 18:35 |
| jhol | you will also need this, if you want to run it: https://github.com/jhol/symbiflow-arch-defs/commits/hlc-out | 18:36 |
| tpb | Title: Commits · jhol/symbiflow-arch-defs · GitHub (at github.com) | 18:36 |
| jhol | this is the command line I'm running: vpr /home/joel/workspace/symbiflow-arch-defs/ice40/devices/tile-routing-virt/arch.merged.xml --device test4 --timing_analysis off big_xor.eblif --gen_post_synthesis_netlist on | 18:37 |
| jhol | ok - got to dash, but I'll check back later | 18:37 |
| digshadow | mithro: the test code just dumped a rebuilt rr_graph | 19:24 |
| digshadow | but it needs checking and suchj | 19:24 |
| digshadow | still, a good milestone | 19:24 |
| mithro | digshadow: What about into / out of vpr? | 19:36 |
| digshadow | I'm trying that now | 19:37 |
| digshadow | I'm not sure if its tracking pin associations properly right now | 19:38 |
| digshadow | so I suspect it will fail | 19:38 |
| digshadow | looks like all of that was preserved | 19:43 |
| digshadow | okay I'll give it a try | 19:43 |
| mithro | digshadow: https://github.com/mithro/rcfiles/blob/master/bin/xmlsort | 20:46 |
| tpb | Title: rcfiles/xmlsort at master · mithro/rcfiles · GitHub (at github.com) | 20:46 |
| mithro | digshadow: But that isn't what I was thinking of... | 20:46 |
| digshadow | sort sounds scary to me | 20:47 |
| digshadow | there are ordering dependencies | 20:47 |
| mithro | digshadow: ET.tostring(pb_type_xml, pretty_print=True).decode('utf-8') -- that what you doing? | 20:47 |
| digshadow | I think? actually that might not be true | 20:47 |
| digshadow | yes | 20:48 |
| digshadow | decoding ascii, but same idea | 20:48 |
| digshadow | ah wait | 20:49 |
| digshadow | think I found issue | 20:49 |
| mithro | See the "serialisation" section of http://lxml.de/tutorial.html | 20:50 |
| tpb | Title: The lxml.etree Tutorial (at lxml.de) | 20:50 |
| digshadow | nope | 20:50 |
| mithro | digshadow: http://lxml.de/FAQ.html#why-doesn-t-the-pretty-print-option-reformat-my-xml-output ? | 20:51 |
| tpb | Title: lxml FAQ - Frequently Asked Questions (at lxml.de) | 20:51 |
| mithro | digshadow: Hrm -> https://github.com/mithro/sphinx-contrib-mithro/blob/master/harden_xml/harden_xml.py#L58-L66 | 20:56 |
| tpb | Title: sphinx-contrib-mithro/harden_xml.py at master · mithro/sphinx-contrib-mithro · GitHub (at github.com) | 20:57 |
| digshadow | mithro: second one did it, thanks! | 20:57 |
| digshadow | kem_: "Message: Missing required child node 'sizing' in parent node 'switch'" upon rr_graph import | 21:23 |
| digshadow | does this need to be a required attribute? | 21:24 |
| digshadow | looks like I can specify 0,0 for reasonable defaults | 21:26 |
| digshadow | I'll open a ticket | 21:26 |
| digshadow | some easy issues if someone wants to submit a patch to vpr | 22:00 |
| digshadow | https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/334 | 22:00 |
| tpb | Title: Improve rr_graph compatibility message · Issue #334 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 22:00 |
| digshadow | https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/333 | 22:00 |
| tpb | Title: rr_graph: switch sizing (and timing?) should be optional · Issue #333 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 22:00 |
| mithro | digshadow: The English in https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/333 is a bit hard to understand? | 22:53 |
| tpb | Title: rr_graph: switch sizing (and timing?) should be optional · Issue #333 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 22:53 |
| digshadow | mithro: it ate some of the tags | 22:54 |
| digshadow | I'll try to fix it up soon | 22:54 |
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