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| mithro | kem_ / jhol: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325 | 01:08 |
|---|---|---|
| tpb | Title: VPR has issues when carry chain inputs are involved in a blocks internal routing · Issue #325 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 01:08 |
| jhol | mithro: I'm just rebasing fasm | 13:03 |
| jhol | mithro, daveshah, kem_: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/327 | 13:07 |
| tpb | Title: Replaced CRLFs with LFs by jhol · Pull Request #327 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 13:07 |
| jhol | I'd like to do something similar with tabs vs. spaces | 13:08 |
| daveshah | jhol: Thanks for doing that! It's been bugging me too | 13:08 |
| daveshah | There were Windows-1252 smart quotes in a file that need removing too | 13:08 |
| daveshah | Lemme find it | 13:08 |
| jhol | oh dear | 13:08 |
| daveshah | jhol: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/pack/hmetis_graph_writer.cpp#L8 | 13:19 |
| tpb | Title: vtr-verilog-to-routing/hmetis_graph_writer.cpp at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 13:19 |
| daveshah | May as well add that to the PR? | 13:19 |
| jhol | sure | 13:20 |
| daveshah | This is borked too: https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vpr/src/place/place_macro.h#L154 | 13:22 |
| tpb | Title: vtr-verilog-to-routing/place_macro.h at master · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 13:22 |
| jhol | daveshah: I found a few more: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/327/commits/d10eef8ade5cf862ea89841f14bad8ffa6db08f3 | 13:25 |
| tpb | Title: Replaced CRLFs with LFs by jhol · Pull Request #327 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 13:25 |
| daveshah | Great, thanks | 13:26 |
| mithro | jhol: morning | 14:03 |
| jhol | mithro: hi! | 14:05 |
| mithro | jhol: Still getting started but feel free to ask questions | 14:05 |
| jhol | sure | 14:05 |
| mithro | jhol: One thing which really helped me with the fasm output was looking at the verilog writer in vpr | 14:06 |
| mithro | jhol: it's code which writes a verilog representation of the place and routed circuit for simulation | 14:06 |
| jhol | so far I've just being polishing up your patches - do you have any introductory information about the format? | 14:07 |
| mithro | jhol: The FASM format? | 14:08 |
| jhol | yeah | 14:08 |
| mithro | jhol: Nope! We are not tied to it either | 14:08 |
| jhol | I can google it if necessary | 14:08 |
| mithro | jhol: No you can't, it doesn't really exist except in people's heads at the moment :-P | 14:08 |
| jhol | yeah ok | 14:09 |
| mithro | jhol: it's basically related to SymbiFlow/prjxray/minitests/roi_harness | 14:09 |
| mithro | jhol: http://prjxray.readthedocs.io/en/latest/db_dev_process/minitests/partial_reconfig_flow.html#fasm-proof-of-concept-using-vivado-partial-reconfig-flow | 14:09 |
| tpb | Title: FASM Proof of Concept using Vivado Partial Reconfig flow Project X-Ray 0.0-623-gb9298a3 documentation (at prjxray.readthedocs.io) | 14:09 |
| mithro | jhol: But as I said, we are very open to change -- if there exists a better format already for the ice40, maybe we look at just using that.... | 14:10 |
| daveshah | The only iCE40 equivalent atm is this https://github.com/cliffordwolf/icestorm/blob/master/icebox/icebox_hlc2asc.py but I'm not really sure I'd recommend it | 14:11 |
| tpb | Title: icestorm/icebox_hlc2asc.py at master · cliffordwolf/icestorm · GitHub (at github.com) | 14:11 |
| mithro | brb | 14:12 |
| mithro | jhol: I wouldn't worry about preserving history for the FASM stuff btw | 14:12 |
| mithro | jhol: did you understand the two parts of the fasm stuff? | 14:15 |
| jhol | https://github.com/jhol/vtr-verilog-to-routing/commits/fasm-rebase | 14:15 |
| tpb | Title: Commits · jhol/vtr-verilog-to-routing · GitHub (at github.com) | 14:15 |
| jhol | -- I squashed the commits together, and then removed irrelevant stuff, then divided it into logical patches | 14:15 |
| jhol | still got a few issues, but it's mostly working | 14:15 |
| mithro | jhol: one part was the generic walker object which made it easier to write things like fasm output | 14:15 |
| jhol | yes | 14:15 |
| mithro | The second part was the actual fasm output part | 14:16 |
| jhol | really should be done with predicates, not a derriving from a walker base class | 14:16 |
| jhol | but it will do the job | 14:16 |
| mithro | With the generic walker part, I think we can rebase a lot of the other output code on top of that walker and it will make it simpler | 14:17 |
| mithro | I'm unsure if it makes sense to send the fasm output upstream until it works for both the ice40 and the artix7? | 14:18 |
| jhol | depends how high the standards are | 14:19 |
| jhol | and how comitted we are to using it | 14:19 |
| jhol | mithro: this compiles ok now. I'm going to start testing it | 14:47 |
| mithro | jhol: Okay, poke me if you want me to look at something... | 14:50 |
| jhol | no problem | 14:50 |
| mithro | jhol: Oh - were are we at with doing a pnr of a picorv32 on virtual fabric? | 14:53 |
| jhol | didn't try it yet - we could do it with the no-carry-chain yosys option | 14:53 |
| jhol | is that something you need? | 14:54 |
| mithro | jhol: Was your carry-chain problem related to the bug I linked over the weekend? | 14:54 |
| jhol | I think so | 14:54 |
| mithro | jhol: This one -> https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325 | 14:54 |
| jhol | so there were two issues | 14:54 |
| tpb | Title: VPR has issues when carry chain inputs are involved in a blocks internal routing · Issue #325 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 14:54 |
| mithro | jhol: The work around for that one seems to be just put the carry input last? | 14:55 |
| jhol | oh I see - didn't know about that | 14:55 |
| jhol | the error I was getting was with counter.v, and it pertains to the SB_CARRY.CO -> LUT4 | 14:55 |
| jhol | in the ice40, the SB_CARRY.CO links to LUT4.I3, but it couldn't figure out how to wire it up | 14:56 |
| jhol | -- even though I'd ostensibly declared the <direct> link for that | 14:56 |
| jhol | the other issue was that it got confused by pack_patterns that cross through modes, but I fixed that by separating the carry chain from the DFFs | 14:58 |
| mithro | jhol: Hrm - I think the mode thing is just a case of having to get the values right....? | 14:59 |
| jhol | I dug into the source code - it has code to make sure your carry-chain doesn't fan out in any way | 15:00 |
| jhol | but it gives you an error because it claims your carry-chain does fan out - when in fact it just has N versions of the carry-chain for N modes | 15:01 |
| mithro | jhol: Hrm - interesting | 15:01 |
| mithro | jhol: Can you log a bug? | 15:01 |
| jhol | I was quite sympathetic to that error | 15:02 |
| jhol | --- because how is it supposed to check the wiring if it could just switcheroo between modes? | 15:02 |
| kem_ | Yep it gets complicated :) Feel free to file a bug though! | 15:03 |
| kem_ | mithro: Can you attach a full architecture and netlist to reproduce #325? | 15:04 |
| jhol | kem_: hi | 15:04 |
| jhol | mithro: in bug 325, was that prompted by this error message: https://paste2.org/jdWgCaKw | 15:08 |
| jhol | you can get it by running this command in tests/ : make ARCH=ice40 DEVICE_TYPE=tile-routing-virt DEVICE=test4 counter.echo | 15:08 |
| jhol | or are you looking at a separate problem? | 15:09 |
| kem_ | mithro: #325 was the carry chain issues: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325 | 15:09 |
| tpb | Title: VPR has issues when carry chain inputs are involved in a blocks internal routing · Issue #325 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 15:09 |
| jhol | yes | 15:09 |
| kem_ | I've always found the symbi-flow makefiles rather indirect. If someone can attach the architecture, netlist and VPR command directly to the issue it would make it much easier for me to take a look :) | 15:13 |
| jhol | kem_: I'll do that if I can confirm it's the same issue | 15:18 |
| kem_ | jhol: Thanks! | 15:18 |
| jhol | kem_: did you see this one?: https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/327 | 15:26 |
| tpb | Title: Replaced CRLFs with LFs by jhol · Pull Request #327 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 15:26 |
| mithro | kem_: Yes, will try to get you one | 16:00 |
| jhol | mithro: hi | 16:08 |
| mithro | jhol: Yesum? | 16:08 |
| jhol | so 2 things: 1. did you see my question about 325? | 16:08 |
| jhol | what error do you get? is it the same of this https://paste2.org/jdWgCaKw ... that I get when I use VPR to build counter.echo ? | 16:09 |
| mithro | jhol: You mean this one -> https://paste2.org/jdWgCaKw -- that is the same error I got with the testarch and carry chain in https://github.com/SymbiFlow/symbiflow-arch-defs/pull/91 | 16:10 |
| tpb | Title: Cleanup and fixes to testarch by mithro · Pull Request #91 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 16:10 |
| jhol | ok - cool, so if I follow the fixes you did there's a good change I get the carry chains working in the ice40 | 16:11 |
| jhol | *good chance | 16:11 |
| jhol | second question: what's the easiest way to get some sample FASM code? | 16:12 |
| mithro | jhol: Hrm -- not sure, maybe ask digshadow? | 16:12 |
| jhol | going to work on bringing the FASM writer into working order | 16:12 |
| jhol | ok | 16:13 |
| jhol | digshadow: ? | 16:13 |
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| mithro | kem_: I of course didn't commit the broken version which was exhibiting the cin problem -- and now I'm having trouble repoing it.... | 18:43 |
| mithro | git reflog to the rescue! | 18:45 |
| mithro | kem_: Test example added in the comment here -> https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325#issuecomment-383683529 | 18:56 |
| tpb | Title: VPR has issues when carry chain inputs are involved in a blocks internal routing · Issue #325 · verilog-to-routing/vtr-verilog-to-routing · GitHub (at github.com) | 18:56 |
| mithro | kem_: Not sure the architecture is particularly "sane".... | 18:57 |
| mithro | digshadow: I think https://github.com/SymbiFlow/symbiflow-arch-defs/pull/91/files is ready to be merged? | 20:20 |
| tpb | Title: Cleanup and fixes to testarch by mithro · Pull Request #91 · SymbiFlow/symbiflow-arch-defs · GitHub (at github.com) | 20:20 |
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