*** tpb has joined #vtr-dev | 00:00 | |
*** digshadow has quit IRC | 01:27 | |
*** digshadow has joined #vtr-dev | 02:10 | |
*** digshadow has quit IRC | 02:30 | |
*** digshadow has joined #vtr-dev | 02:44 | |
*** digshadow has quit IRC | 02:52 | |
*** digshadow has joined #vtr-dev | 03:41 | |
jhol | digshadow: no nothing further than that - but it does plug into the existing test-suite nicely | 07:17 |
---|---|---|
jhol | so it beats icebox-rr_graph-import.py | 07:18 |
jhol | if you're working on routing, make sure you read these two thoroughly if you didn't already: http://www.clifford.at/icestorm/logic_tile.html , http://www.clifford.at/icestorm/io_tile.html | 07:20 |
tpb | Title: Project IceStorm LOGIC Tile Documentation (at www.clifford.at) | 07:20 |
jhol | also - a little heads up that there are a few nets not mentioned in those docs, that are listed in the tile docs: http://www.clifford.at/icestorm/bitdocs-1k/tile_2_16.html | 07:21 |
tpb | Title: Project IceStorm iCE40 HX1K LOGIC Tile (2 16) (at www.clifford.at) | 07:21 |
*** digshadow-c has joined #vtr-dev | 07:24 | |
digshadow | jhol: further than what? I might be missing some backlog | 07:24 |
digshadow | jhol: I did read over those | 07:25 |
jhol | cool cool | 07:25 |
digshadow | not the latter though | 07:25 |
jhol | well the point is that the written documentation in icestorm doesn't cover everything, there's more info in the tile docs | 07:25 |
jhol | it might be helpful to add details to the docs about the finer details of the routing | 07:26 |
digshadow | I did a pr for some grammer fixes | 07:26 |
digshadow | we'll see if that gets merged first ;) | 07:26 |
jhol | nice - thanks! | 07:26 |
digshadow | what was the message before the one direct to me? | 07:27 |
jhol | "jhol: I see you added a boiler plate script in ice40/utils, did it go any further than that?" | 07:27 |
digshadow | oh gotcha | 07:28 |
digshadow | not too much new on my side. I think I pushed out some very small things | 07:28 |
digshadow | but really WIP | 07:28 |
digshadow | mostly just reading docs and going over existing stuff with mithro | 07:29 |
jhol | so one nice thing is that with the new script, we're not building an rr_graph from scratch, so all the code related to <block_types> and <grid> can be scrapped | 07:29 |
jhol | so it's just the channels stuff: <channels>, <switches>, <segments>, and the graph stuff <rr_nodes>, <rr_edges> | 07:29 |
digshadow | are you going to poke at it today | 07:30 |
jhol | I'm going to focus on resurrecting mithro's old fake-routed ice40 | 07:30 |
digshadow | k | 07:30 |
digshadow | I did run the tests dir today with ARCH=ice40 | 07:31 |
digshadow | and it did run some tests without failing for what that is worth | 07:31 |
jhol | yeah - well part of that is that I think it defaults to the "ice4" architecture, which looks a bit broken | 07:31 |
jhol | the DEVICE=ice40-virt, DEVICE=hx0k seems to be the same idea as ice4, but less buggy | 07:32 |
jhol | ice4 should probably be deleted, because there's no point trying to keep it in sync with ice40-virt:hx0k | 07:33 |
jhol | * DEVICE=ice40-virt, DEVICE_TYPE=hx0k | 07:34 |
jhol | digshadow: did you see this yet: https://knielsen.github.io/ice40_viewer/ice40_viewer.html ? | 07:37 |
tpb | Title: ICE40 layout viewer (at knielsen.github.io) | 07:37 |
digshadow | I heard it exists, I haven't seen it | 07:37 |
jhol | yah, fun to play with to get a feel for what's there | 07:38 |
digshadow | pretty cool | 07:38 |
digshadow | hmm wonder if we could import this into VPR GUI | 07:39 |
jhol | that would be cool | 07:39 |
jhol | I would say you have the harder slice of the job, but at least mithro is with you to help | 07:40 |
jhol | the other piece of the puzzle I forgot to mention is that we'll need to write a converter that can take the VPR output and convert it into the input for icebox for the bitstream output | 07:41 |
jhol | that's a task for whoever gets there first :) | 07:41 |
digshadow | yes, less worried about that | 07:41 |
digshadow | I'm presumably that will be relatively straightforward, but we'll see | 07:41 |
digshadow | have people showing up early tomorrow morning, need to go to sleep | 07:43 |
digshadow | i'll check back in the morning | 07:43 |
jhol | yeah no worries! | 07:43 |
jhol | sleep well | 07:43 |
mithro | Morning everyone | 13:59 |
mithro | jhol: heyo | 14:00 |
*** mithro has quit IRC | 14:15 | |
*** mithro has joined #vtr-dev | 14:16 | |
jhol | mithro hi! | 14:18 |
mithro | jhol: How goes things? | 14:19 |
jhol | interesting things - I've been going through your old branch, and comparing to master | 14:19 |
jhol | I got the old branch to route - with a few tweaks here and there | 14:21 |
jhol | but interestingly, the mast branch can route with very little tweaking | 14:21 |
jhol | https://ibin.co/3xuWaYl6dx9v.png | 14:21 |
jhol | https://ibin.co/3xuWoIUPwFtE.png | 14:22 |
jhol | that's it routing ff.blif | 14:22 |
mithro | jhol: Well things that are being tested on Travis should be working :-P | 14:23 |
jhol | well it seems to be working alright | 14:23 |
mithro | https://travis-ci.org/SymbiFlow/symbiflow-arch-defs/builds/363359771 | 14:23 |
mithro | https://travis-ci.org/SymbiFlow/symbiflow-arch-defs/builds/362411931 | 14:24 |
jhol | sure! | 14:24 |
mithro | https://www.irccloud.com/pastebin/AMNm7ch1/ | 14:24 |
tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 14:24 |
jhol | so couple of questions: | 14:24 |
jhol | I've been comparing the pb_type structure between mithro/master-ice40-local-route and master | 14:25 |
jhol | https://notehub.org/xkf3n | 14:25 |
jhol | so the main difference being how the local tracks etc. are represented | 14:25 |
jhol | so from what you said, it will be necessary to go back to the old structure, where the local routing is done with segments | 14:26 |
mithro | jhol: Yeah | 14:26 |
jhol | -- except now I'm confused, because the structure in master is actually routing | 14:26 |
mithro | jhol: https://github.com/mithro/symbiflow-arch-defs/blob/rr_graph_lib_new/ice40/cells/plb/plb.pb_type.xml | 14:28 |
tpb | Title: symbiflow-arch-defs/plb.pb_type.xml at rr_graph_lib_new · mithro/symbiflow-arch-defs · GitHub (at github.com) | 14:28 |
mithro | jhol: Do you recall I said not to trust anything I say? :-P | 14:29 |
jhol | haha! | 14:29 |
mithro | jhol: See how that has the comment at the bottom? | 14:29 |
jhol | ahh yes you told me about that one | 14:30 |
jhol | and what happens if you uncomment it? VPR crashes? | 14:30 |
mithro | jhol: So at some point in the past that was a top level pb_type | 14:31 |
jhol | ok well it looks like I need to reassess the pros and cons of the different structures, because at the moment I'm liking the master structure more, and VPR doesn't seem to mind it | 14:34 |
mithro | jhol: Then I started https://github.com/mithro/symbiflow-arch-defs/blob/rr_graph_lib_new/ice40/tiles/plb/plb.pb_type.xml which pushes a lot of the routing into the tile rather then the rr_graph | 14:34 |
tpb | Title: symbiflow-arch-defs/plb.pb_type.xml at rr_graph_lib_new · mithro/symbiflow-arch-defs · GitHub (at github.com) | 14:34 |
jhol | really the routing should be factored out into an include, because it's identical in the RAM tiles | 14:35 |
mithro | jhol: Possibly | 14:35 |
jhol | either that, or put the RAMs and the PLBs in one common <pb_type> | 14:36 |
mithro | jhol: If you can get picorv32 to work, I | 14:37 |
mithro | jhol: If you can get picorv32 to work, I'm not tied to an approach... | 14:38 |
jhol | ahh true - not a fair test! | 14:38 |
jhol | so this leads me on to the next question: eblif | 14:38 |
jhol | write_eblif doesn't seem to be present in my master build of yosys | 14:39 |
*** kem_ has quit IRC | 14:39 | |
*** kem_ has joined #vtr-dev | 14:39 | |
mithro | jhol: write_blif -- http://www.clifford.at/yosys/cmd_write_blif.html | 14:39 |
tpb | Title: Yosys Open SYnthesis Suite :: Command Reference :: write_blif (at www.clifford.at) | 14:39 |
mithro | jhol: See the options at the end | 14:40 |
jhol | oh ok - looks like the makefiles need tweaking then | 14:41 |
jhol | ok - one other question: I see both pio-tb and pio-lr hanging around, but they both got replaced by PAD | 14:42 |
mithro | Possibly | 14:42 |
jhol | so is there no need for different PIO types of the horizontal and vertical edges? | 14:43 |
mithro | jhol: Possibly because of the different way the routing inside a PIO tile works | 14:43 |
jhol | exactly - so it would seem like a regression to describe the whole the whole thing with just a "PAD" tile | 14:44 |
jhol | again, if you don't know off the top of your head, I'll investigate myself | 14:44 |
mithro | http://www.clifford.at/icestorm/io_tile.html | 14:44 |
tpb | Title: Project IceStorm IO Tile Documentation (at www.clifford.at) | 14:44 |
jhol | yeah looks like they should be different | 14:45 |
mithro | daveshah: http://www.clifford.at/icestorm/ultraplus.html -- do you have a "tile map" for the ultraplus? Like the one which you see http://www.clifford.at/icestorm/bitdocs-8k/ ? | 14:48 |
tpb | Title: Project IceStorm UltraPlus Features Documentation (at www.clifford.at) | 14:48 |
daveshah | mithro: No, I need to create one at some point. | 14:48 |
mithro | daveshah: I'm looking at http://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40Ultra | 14:49 |
tpb | Title: iCE40 Ultra / UltraLite / UltraPlus - Lattice Semiconductor (at www.latticesemi.com) | 14:49 |
daveshah | Official tile map: https://user-images.githubusercontent.com/52649/27361488-845fe5fc-55dc-11e7-8a24-c2d2299d6eef.png | 14:49 |
jhol | pretty | 14:49 |
daveshah | The routing inside the DSP and IP connect tiles are the same as in a logic tile AFAICS | 14:49 |
daveshah | Those tiles are the tiles at the side (DSPs are 4 tiles) | 14:50 |
mithro | daveshah: There seems to be a 5k LUT part which doesn't have a part number? :-P | 14:50 |
daveshah | What? | 14:51 |
daveshah | Is that not the ultraplus | 14:51 |
daveshah | Oh, I know that table | 14:51 |
daveshah | It's borked and offset by one | 14:51 |
mithro | jhol: Well do reach out if you get any further | 15:23 |
jhol | going to try picorv32 and see how that pans out | 15:27 |
*** digshadow has quit IRC | 15:41 | |
mithro | jhol: Great! We should make sure it is eventually done in a way that we can continually test it as part of the repo -- but for now I just want to see what happens :-) | 15:43 |
*** digshadow has joined #vtr-dev | 15:44 | |
jhol | master-ice40-local-remote doesn't seem able to route led.v | 16:01 |
jhol | lots of errors - got to dig into what's going wrong | 16:02 |
mithro | jhol: Great! | 16:38 |
jhol | digshadow: just starting a 1h30 stint to finish off the day | 19:02 |
jhol | all going well with your stuff? | 19:02 |
digshadow | jhol: taking care of some other stuff right now, but I should get back to it soon | 19:05 |
jhol | no worries! | 19:05 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!