Thursday, 2018-04-05

*** tpb has joined #vtr-dev00:00
*** digshadow has quit IRC03:23
*** digshadow has joined #vtr-dev04:53
*** tpb has joined #vtr-dev08:13
*** vtrbot has quit IRC08:15
*** vtrbot has joined #vtr-dev08:22
kem_Defining terminology/concepts is an area where VTR's documentation is weak and could be improved13:41
kem_I'd be very happy to merge documentation PR's which improve things13:43
kem_Most of the terminology comes from the FPGA Architecture research literature.13:45
kem_The classic reference (which covers both FPGA Architecture and VPR) is: https://dl.acm.org/citation.cfm?id=55352313:47
tpbTitle: Architecture and CAD for Deep-Submicron FPGAs (at dl.acm.org)13:47
*** digshadow has left #vtr-dev16:49
*** digshadow has joined #vtr-dev18:43
digshadowmithro: reading through the original arch.xml paper, it talks about representing fractionable LUTs as clusters. I take it this would work easily well for Xilinx BRAM which can be fractured into 2x18 or 1x36?22:47
mithrodigshadow: Yes23:20

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!