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| digshadow | mithro: http://docs.verilogtorouting.org/en/latest/tutorials/timing_simulation/ | 21:56 |
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| tpb | Title: Post-Implementation Timing Simulation Verilog-to-Routing 8.0.0-dev documentation (at docs.verilogtorouting.org) | 21:57 |
| digshadow | timing sim demo is in modelsim, wonder why that was chosen over something FOSS like iverilog / gtkwave | 21:57 |
| digshadow | daveshah: have you ever tried SDF in iverilog? looks like it supports it | 22:02 |
| digshadow | Sounds like maybe I should try to target .sdf out from the prjxray timing analysis | 22:02 |
| daveshah | No, I haven't used SDF for anything other than reverse engineering ice40 timings | 22:03 |
| daveshah | It has worked well for that though | 22:03 |
| mithro | digshadow: No idea - kem_ can probably answer about modelsim - I'm guessing probably speed or compatibility with some type of models? | 22:13 |
| digshadow | daveshah: I was looking at hte ice40 stuff. it looks like its sdf like but not quite as its missing () | 22:29 |
| digshadow | mithro: the example has logic types in the testbench. I'll see if I can get it to run with iverilog | 22:30 |
| daveshah | digshadow: from memory that's Clifford's intermediate format, what you get raw out of icecube is proper SDF | 22:31 |
| digshadow | daveshah: okay thanks I'll take a look | 22:34 |
| digshadow | also FYI I found a small error in the tutorial, making a PR | 22:34 |
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