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| mithro | kem_: VPR wouldn't really be suitable for doing PnR for "sum of products" style devices (rather than LUT style), right? | 19:03 |
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| kem_ | mithro: VPR isn't strictly tied to LUTs as the logic implementation | 22:41 |
| kem_ | mithro: For SoP devices (e.g. PLAs) it really depends on whether you actually need PnR to optimize something, and where you draw the line between logic synthesis and PnR | 22:43 |
| kem_ | mithro: You could theoretically have logic synthesis spit out a netlist of ANDs/ORs and nets connecting them. If you then described the architecture (e.g. placement sites, routing graph) then VPR could theoretically then be used to do PnR | 22:45 |
| kem_ | mithro: My experience with such devices is very limited, so I'm not sure a full-blown PnR is really necessary (e.g. is there something to optimize post-synthesis or is everything already fully determined) | 22:48 |
| kem_ | mithro: By the time you get to something more complex like a CPLD it probably starts to make more sense | 22:52 |
| mithro | kem_: It was a thought experiment about what is the simplest *real* device we could generate an actual bitstream for | 22:53 |
| mithro | kem_: Do you have any contact with http://thedonnellycentre.utoronto.ca/ ? | 23:18 |
| tpb | Title: Donnelly Centre for Cellular and Biomolecular Research (at thedonnellycentre.utoronto.ca) | 23:18 |
| mithro | kem_: Pondering using their http://js.cytoscape.org/ library for some rendering of interconnection stuff | 23:18 |
| tpb | Title: Cytoscape.js (at js.cytoscape.org) | 23:18 |
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